How does Rev.C organize the 256M LPDDR memory?

In the new version of Beagleboard REV.C, it was deployed Micron 256M
LPDDR + 512M NAND. I would like to know which type of Micron current
product? In the documentation of OMAP3530 memory subsystem (http://
focus.ti.com/lit/ug/sprufa1c/sprufa1c.pdf), I only found the memory
stack configuration with one 32bit LPDDR on CS0. But in the Micron
current product for Beagleboard (http://www.micron.com/products/mcps/
beagleboard_partlist), all of 2Gbit memory product for Beagleboard is
combined the dual 1Gbit 32bit LPDDR in one MCP(NAND+LPDDR) package,
example for "MT29C4G48MAPLCJI-6 IT"
my question is how does the Beagleboard Rev.C organized the memory
stack? wether CS0 addressing first LPDDR and CS1 addressing second
LPDDR?

Where can I get the source code of xloader for Beagleboard Rev.C, and
the Rev.C was supported by u-boot and Linux Kernel?

vortune <vortune@gmail.com> writes:

my question is how does the Beagleboard Rev.C organized the memory
stack? wether CS0 addressing first LPDDR and CS1 addressing second
LPDDR?

There is 128MB on each of CS0 and CS1.

Where can I get the source code of xloader for Beagleboard Rev.C, and
the Rev.C was supported by u-boot and Linux Kernel?

It is fully supported by current u-boot and kernel.