How is the ethernet port connected to the main CPU on BBAI-64

I tried to understand how the physical ethernet port on BBAI-64 was connected to the main A72 CPUs. From the schematics it looks like it is connected to the MCU_RGMII interface. How (and where) is the setup for communication between the main island CPU and the MCU island? How are the CPSWxG switches involved?

Bonus question: is it possible to wire a MAC2MAC connection between the CPSW9G and CPSW2G on the bbai64?

Second bonus question: is it possible to load the TI EthFirmware on a R5F MCU in the main island?

Maybe this helps on bonus question 2? J721e u-boot allows firmware to be loaded…

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