I tried to understand how the physical ethernet port on BBAI-64 was connected to the main A72 CPUs. From the schematics it looks like it is connected to the MCU_RGMII interface. How (and where) is the setup for communication between the main island CPU and the MCU island? How are the CPSWxG switches involved?
Bonus question: is it possible to wire a MAC2MAC connection between the CPSW9G and CPSW2G on the bbai64?
Second bonus question: is it possible to load the TI EthFirmware on a R5F MCU in the main island?
Hi @Jonas_Bulow - I’ve just been investigating the same thing.
From what I see in schematics the physical port we have on BB-AI64 is coming from the MCU domain. This confuses me since I presumed that Main / Safety domains were separated. Moreover, it does appear that the MAIN_RGMII5 and MAIN_RGMII6 are connected thru to P8/P9 headers…(maybe I’m wrong about that but I’ve found at least some of them on headers)…
I can only assume that the internal CPSW9G / 2G are somehow connected inside the chip? Thus data going in / out MCU_RGMII hits the switch fabric and propagates to MAIN domain?
Further, it appears that one could build a shield to expose 2(?) ports from MAIN_RGMII5 and MAIN_RGMII6?
I could be wrong about everything I just wrote, but would happy if someone could explain it!
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