How to/How many IO are directly available to FPGA design on BeagleVFire

BeagleV
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1

I have a verilog project on BeagleV-Fire that requires 31 pins: 20 inputs and 11 outputs.
What pins are available as outputs and inputs on P8 and P9 that can be connected to FPGA fabric?

Following the guide, I am connecting my pins from my module like so:

assign GPIO_OE_net_0  = { 16'b0101111111111100, GPIO_OE };
assign GPIO_OUT_net_0 = { 1'b0 , MISO, 1'b0, AERIN_REQ, AEROUT_ADDR[7], AEROUT_ADDR[6], AEROUT_ADDR[5],
                        AEROUT_ADDR[4], AEROUT_ADDR[3], AEROUT_ADDR[2], AEROUT_ADDR[1], AEROUT_ADDR[0], AERIN_ACK, 2'b00, GPIO_OUT };

Is this the correct way to do so? What I believe I understand I am doing is enabling and connecting pins P8_32-41 and P8_43.

What is the method to configure the other pins I need as inputs?

2

P8_26 to P8_46 are GPIOs and can be configured as either.
P9_11 to P9_18 and P9_21 to P9_31 are also GPIO.

All of this can be seen in the schematic which amongst other things can be found here:
BeagleV-Fire / beaglev-fire · GitLab (openbeagle.org)

As to the “correct” way, I would say that entirely depends on what you want it to do.
The PolarFire is completely flexible when it comes to steering the pins.

With a FPGA, you have complete autonomy.

3

You could probably also use P8_15 to P8_25, just know they run through level-shifters
and those can be a bit temperamental if not treated correctly.