HSS Build Failed

Hello,

I am trying to get the default Libero design and I am having trouble getting the HSS to build. I am using GitBash to go through the “Exploring Gateware Design with Libero” demo and the source script that bustedwing created. I am getting the error:

riscv64-unknown-elf-gcc.exe: error: bui: No such file or directory
make: *** [Makefile:137: hss-l2scratch.elf] Error 1
!!! Error: Hart Soft Service build failed !!!

$ python build-bitstream.py ./build-options/default.yaml
Running on Windows host
Windows Subsystem for Linux installed
Found device tree compiler:  Version: DTC 1.6.1

Design version:  2004
Design version: 2004
================================================================================
                              Initialize workspace
================================================================================

  The FlashPro Express bitstream programming job files will be stored in
  directory: ./bitstream/FlashProExpress

================================================================================
                                 Clone sources
================================================================================

HSS checked out at commit v2025.03
Applying: Disable annoying debug message
Applying: Bring back old DESIGNVER formatting
================================================================================
                            Generate Device Tree Overlays
================================================================================

Board options path: .\board-options\board-selection.yaml
The board selected is: mpfs-beaglev-fire
Path to dtso files:  device-tree-overlay
  Device tree overlay selected:
    component:                 CAPE
    build option:              DEFAULT
    device tree overlay file:  cape-gpios.dtso
  Device tree overlay selected:
    component:                 CAPE
    build option:              DEFAULT
    device tree overlay file:  leds.dtso
  Device tree overlay selected:
    component:                 M2
    build option:              DEFAULT
    device tree overlay file:  pcie.dtso
number of gateware device tree overlays:  3
C:\Cadence\SPB_22.1\Beagle_m2\gateware\work\dtbo\context-0\CAPE\cape-gpios.dtbo
C:\Cadence\SPB_22.1\Beagle_m2\gateware\work\dtbo\context-0\CAPE\leds.dtbo
C:\Cadence\SPB_22.1\Beagle_m2\gateware\work\dtbo\context-0\M2\pcie.dtbo
b'MCHP\x1c\x00\x00\x00\x00\x00\x01\x00\x10\x00\x00\x00\x03\x00\x00\x008\x00\x00\x00*\x0b\x00\x00\xf2\n\x00\x00*\x0b\x00\x00\xd0\x11\x00\x00\xa6\x06\x00\x00\xd0\x11\x00\x00<\x13\x00\x00l\x01\x00\x00'
The board selected is: mpfs-beaglev-fire
|| -- Board: mpfs-beaglev-fire --||-- Die: MPFS025T --||-- Package:  FCVG484 --||-- Die voltage:  1.0 --||-- Part range:  EXT  --||
MSS folder path: .\sources\MSS_Configuration\MPFS025T\FCVG484\mpfs-beaglev-fire
Selected config file: .\sources\MSS_Configuration\MPFS025T\FCVG484\mpfs-beaglev-fire\MSS_Configuration.cfg
================================================================================
                          Generating MSS configuration
================================================================================

INFO: Fabric programming is required to apply changes to following FICs settings. FIC_0 (AXI4) , FIC_1 (AXI4) , FIC_2 (AXI4) and FIC_3 (APB).
INFO: MSS PLL - Input Reference Clock frequency 125.000 MHz
    +------------------------------+-------------------------+------------------------------+
    | Output Clock Name            | Required (MHz)          | Integer solution (MHz)       |
    +------------------------------+-------------------------+------------------------------+
    | Output0 Frequency (CPU)      | 600.000                 | 600.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output1 Frequency (Crypto)   | N/A                     | N/A                          |
    +------------------------------+-------------------------+------------------------------+
    | Output2 Frequency (EMMC/SD)  | 200.000                 | 200.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output3 Frequency (CAN)      | 8.000                   | 8.000                        |
    +------------------------------+-------------------------+------------------------------+
INFO: DDR PLL - Input Reference Clock frequency 125.000 MHz
    +------------------------------+-------------------------+------------------------------+
    | Output Clock Name            | Required (MHz)          | Integer solution (MHz)       |
    +------------------------------+-------------------------+------------------------------+
    | Output0 Frequency            | 800.000                 | 800.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output1 Frequency            | 400.000                 | 400.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output2 Frequency            | 800.000                 | 800.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output3 Frequency            | 800.000                 | 800.000                      |
    +------------------------------+-------------------------+------------------------------+
INFO: SGMII PLL - Input Reference Clock frequency 125.000 MHz
    +------------------------------+-------------------------+------------------------------+
    | Output Clock Name            | Required (MHz)          | Integer solution (MHz)       |
    +------------------------------+-------------------------+------------------------------+
    | Output0 Frequency            | 625.000                 | 625.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output1 Frequency            | 625.000                 | 625.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output2 Frequency            | 625.000                 | 625.000                      |
    +------------------------------+-------------------------+------------------------------+
    | Output3 Frequency            | 625.000                 | 625.000                      |
    +------------------------------+-------------------------+------------------------------+
INFO: Successfully generated xml file to 'C:\Cadence\SPB_22.1\Beagle_m2\gateware\work\MSS/PF_SOC_MSS_mss_cfg.xml'
INFO: Successfully generated MSS configuration report to 'C:\Cadence\SPB_22.1\Beagle_m2\gateware\work\MSS\PF_SOC_MSS_Report.html'
INFO: Successfully generated MSS component to 'C:\Cadence\SPB_22.1\Beagle_m2\gateware\work\MSS/PF_SOC_MSS.cxz'
INFO: FPGA Fabric programming is required.
================================================================================
                      Build Hart Software Services (HSS)
================================================================================

Target board: mpfs-beaglev-fire
Cleaning up existing XML files in ./sources\HSS\boards\mpfs-beaglev-fire\soc_fpga_design\xml
Removing ./sources\HSS\boards\mpfs-beaglev-fire\soc_fpga_design\xml\PF_SOC_MSS_mss_cfg.xml
Copying new XML file from work\MSS\PF_SOC_MSS_mss_cfg.xml to sources\HSS\boards\mpfs-beaglev-fire\soc_fpga_design\xml\PF_SOC_MSS_mss_cfg.xml
INFO: Windows detected
mpfs-beaglev-fire selected
INFO: NOTICE: enabling -flto (which means stack protection is disabled)
INFO: Expected mpfsBootmodeProgrammer.jar version v3.6 but found
INFO: This version of the HSS relies on SoftConsole v2021.3 or later
INFO: Windows detected
mpfs-beaglev-fire selected
INFO: NOTICE: enabling -flto (which means stack protection is disabled)
INFO: Expected mpfsBootmodeProgrammer.jar version v3.6 but found
INFO: This version of the HSS relies on SoftConsole v2021.3 or later
 MPFSCFGGEN    boards/mpfs-beaglev-fire/soc_fpga_design/xml/PF_SOC_MSS_mss_cfg.xml
Input XML file: C:\Cadence\SPB_22.1\Beagle_m2\gateware\sources\HSS\boards\mpfs-beaglev-fire\soc_fpga_design\xml/PF_SOC_MSS_mss_cfg.xml
Hardware configuration header files created in directory: C:\Cadence\SPB_22.1\Beagle_m2\gateware\sources\HSS\build\boards\mpfs-beaglev-fire/fpga_design_config
 GENCONFIG
INFO: SoftConsole on Windows detected, adding  C:\Cadence\SPB_22.1\Beagle_m2\gateware\sources\HSS\thirdparty\Kconfiglib to Python sys.path
 CC        build/application/hart0/hss_state_machine.o
 CC        build/application/hart0/hss_clock.o
 CC        build/application/hart0/hss_registry.o
 CC        build/baremetal/drivers/mss/mss_usb/mss_usb_common_cif.o
 CC        build/baremetal/drivers/mss/mss_usb/mss_usb_device.o
 CC        build/baremetal/drivers/mss/mss_usb/mss_usb_device_cif.o
 CC        build/baremetal/drivers/mss/mss_usb/mss_usb_device_msd.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/hal/hal_irq.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/drivers/mss/mss_gpio/mss_gpio.o
 CC        build/services/beu/beu_service.o
 CC        build/services/boot/hss_boot_service.o
 CC        build/services/boot/hss_boot_pmp.o
 CC        build/services/boot/gpt.o
 CC        build/services/ddr/ddr_service.o
 CC        build/services/ddr/ddr_api.o
 CC        build/services/goto/goto_service.o
 CC        build/services/healthmon/healthmon_service.o
 CC        build/services/healthmon/healthmon_monitors_weak.o
 CC        build/services/gpio_ui/gpio_ui_service.o
 CC        build/services/gpio_ui/gpio_ui_api.o
 CC        build/services/ipi_poll/ipi_poll_service.o
 CC        build/services/opensbi/opensbi_service.o
 CC        build/thirdparty/opensbi/lib/utils/irqchip/plic.o
 CC        build/thirdparty/opensbi/lib/utils/libfdt/fdt.o
 CC        build/thirdparty/opensbi/lib/utils/libfdt/fdt_ro.o
 CC        build/thirdparty/opensbi/lib/utils/libfdt/fdt_rw.o
 CC        build/thirdparty/opensbi/lib/utils/libfdt/fdt_wip.o
 CC        build/thirdparty/opensbi/lib/utils/libfdt/fdt_addresses.o
 CC        build/thirdparty/opensbi/lib/utils/fdt/fdt_fixup.o
 CC        build/thirdparty/opensbi/lib/utils/fdt/fdt_helper.o
 CC        build/thirdparty/opensbi/lib/sbi/riscv_asm.o
 CC        build/thirdparty/opensbi/lib/sbi/riscv_atomic.o
 CC        build/thirdparty/opensbi/lib/sbi/riscv_locks.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_bitmap.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_bitops.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_console.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_domain.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_emulate_csr.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_fifo.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_hart.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_hsm.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_illegal_insn.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_init.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ipi.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_irqchip.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_math.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_misaligned_ldst.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_platform.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_pmu.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_scratch.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_string.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_system.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_timer.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_tlb.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_trap.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_unpriv.o
 CC        build/thirdparty/opensbi/lib/utils/timer/aclint_mtimer.o
 CC        build/thirdparty/opensbi/lib/utils/ipi/aclint_mswi.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_base.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_hsm.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_ipi.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_legacy.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_pmu.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_rfence.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_srst.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_time.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_ecall_vendor.o
 CC        build/services/opensbi/opensbi_ihc_ecall.o
 CC        build/services/opensbi/opensbi_rproc_ecall.o
 CC        build/services/opensbi/platform.o
 CC        build/services/opensbi/opensbi_ecall.o
 CC        build/services/reboot/reboot_service.o
 CC        build/services/scrub/scrub_service.o
 CC        build/services/sgdma/sgdma_service.o
 CC        build/services/startup/startup_service.o
 CC        build/services/tinycli/tinycli_api.o
 CC        build/services/tinycli/tinycli_service.o
 CC        build/services/tinycli/tinycli_hexdump.o
 CC        build/services/usbdmsc/flash_drive/flash_drive_app.o
 CC        build/services/usbdmsc/usbdmsc_api.o
 CC        build/services/usbdmsc/usbdmsc_service.o
 CC        build/services/usbdmsc/flash_drive/usb_user_descriptors.o
 CC        build/services/wdog/wdog_service.o
 CC        build/modules/compression/hss_decompress.o
 CC        build/thirdparty/miniz/miniz.o
 CC        build/modules/ssmb/ipi/ssmb_ipi.o
 CC        build/application/hart0/hss_init.o
 CC        build/application/hart0/hss_main.o
 CC        build/application/hart1-4/u54_handle_ipi.o
 CC        build/application/hart1-4/u54_state.o
 CC        build/boards/mpfs-beaglev-fire/hss_uart_init.o
 CC        build/boards/mpfs-beaglev-fire/uart_device_list.o
 CC        build/boards/mpfs-beaglev-fire/hss_board_init.o
 CC        build/boards/mpfs-beaglev-fire/hss_logo_init.o
 CC        build/init/hss_ddr_init.o
 CC        build/init/hss_boot_init.o
 CC        build/init/hss_sys_setup.o
 CC        build/init/hss_usb_init.o
 CC        build/init/hss_ihc_init.o
 CC        build/init/hss_pcie_init.o
 CC        build/init/hss_opensbi_init.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/drivers/mss/mss_pdma/mss_pdma.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/drivers/mss/mss_mmc/mss_mmc.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/drivers/mss/mss_mmc/mss_mmc_if.o
 CC        build/baremetal/drivers/fpga_ip/miv_ihc/miv_ihc.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/drivers/mss/mss_mmuart/mss_uart.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/drivers/mss/mss_sys_services/mss_sys_services.o
 CC        build/baremetal/drivers/mss/mss_watchdog/mss_watchdog.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_mpu.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_peripherals.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_plic.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_beu.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_l2_cache.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_util.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_nwc_init.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_io.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_pll.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/mss_pmp.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_sgmii.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/startup_gcc/system_startup.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_ddr.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.o
 CC        build/services/mmc/mmc_api.o
 CC        build/modules/debug/hss_debug.o
 CC        build/modules/debug/hss_perfctr.o
 CC        build/modules/misc/assert.o
 CC        build/modules/misc/csr_helper.o
 CC        build/modules/misc/c_stubs.o
 CC        build/modules/misc/hss_crc16.o
 CC        build/modules/misc/hss_crc32.o
 CC        build/modules/misc/hss_memcpy_via_pdma.o
 CC        build/modules/misc/hss_progress.o
 CC        build/modules/misc/device_serial_number.o
 CC        build/modules/misc/design_version_info.o
 CC        build/modules/misc/uart_helper.o
 CC        build/modules/misc/hss_trigger.o
 CC        build/modules/misc/hss_memtest.o
 CC        build/application/crt.o
 CC        build/baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/startup_gcc/mss_utils.o
 CC        build/thirdparty/opensbi/lib/sbi/riscv_hardfp.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_expected_trap.o
 CC        build/thirdparty/opensbi/lib/sbi/sbi_hfence.o
 CARRAY    thirdparty/opensbi/lib/sbi/sbi_ecall_exts.carray
 CC        build/services/opensbi/opensbi_ecall_exts.o
 CPP       boards/mpfs-beaglev-fire/hss-l2scratch.ld
 LD        hss-l2scratch.elf
riscv64-unknown-elf-gcc.exe: error: bui: No such file or directory
make: *** [Makefile:137: hss-l2scratch.elf] Error 1
!!! Error: Hart Soft Service build failed !!!

Upon researching online, the issue maybe because of my PATH being incorrect. I tried installing and setting a new path, but I am running into the same error. Running riscv64-unknown-elf-gcc --version gets me:

riscv64-unknown-elf-gcc.exe (SiFive GCC-Metal 10.2.0-2020.12.8) 10.2.0
Copyright (C) 2020 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

I am not sure where to go from here. Please let me know if I can provide anymore information. Thanks.

Small update. I am now trying to build the environment on Ubuntu 20.04. I have completed all the steps but am getting a different error for HSS:

Hardware configuration header files created in directory: /home/test/Beagle_m2/test/gateware/sources/HSS/build/boards/mpfs-beaglev-fire/fpga_design_config
 GENCONFIG
 CC        build/application/hart0/hss_state_machine.o
In file included from application/hart0/hss_state_machine.c:22:
./include/hss_debug.h:44:14: fatal error: inttypes.h: No such file or directory
   44 | #    include "inttypes.h"
      |              ^~~~~~~~~~~~
compilation terminated.
make: *** [application/rules.mk:184: build/application/hart0/hss_state_machine.o] Error 1
!!! Error: Hart Soft Service build failed !!!

Any info on either issue would be greatly appreciated.

libstdc++-12-dev in Debian Bookworm is available for cross.

I am not so sure about Ubuntu Distros. I can test later. My Ubuntu dev. desktop is in a state of failure. I need to update it soon.

Try apt search libstdc++- or another command to search apt for your files available.

Look at which exact cross builds the given inttypes.h preprocessor directive via apt.

Or the command, sudo apt search libstdc can work.

Seth

P.S. Those are a set of Linux commands to get used to currently. You should be able to mix and match to see what is available and depending on your architecture, you can then pick what is available for your arch. For instance, amd64 or arm64 or whatever should be available. To find this I went to https://pubs.opengroup.org/onlinepubs/009696899/basedefs/inttypes.h.html to do some research and then off to the search bar for Debian.

So, in the search bar in the browser, look at inttypes.h and Debian for review.

Thanks for the reply Seth. I will continue to look into it when I get the chance. For now, I was able to use GitBash and bustedwing’s repo using the custom yaml. I still have not been successful in doing the same with the git from the demo.

A separate issue I have encountered is the device tree overlay not working. It seems even with default parameters, no device tree overlay is on the board once the .sh script finishes. I am not sure if this is an issue with bustedwing’s repo or not. I will continue investigating. For context, I am trying to change the device code for the onboard pcie connector (0x1156 → something else).

1 Like

Hello, I have been having the same problem for a while now. Did you manage to solve it and how did you do it? Thanks.

Instead of getting bogged down with some unrelated issue,
have you tried to just check in your design changes and let the CI run the build?

I know that the Libero setup can be somewhat temperamental,
so perhaps just bypass that completely?

I can see you’ve tried to set up on WSL…
No experience with that, I went straight to an Ubuntu 22.04 VM and it’s behaving amiably.

Fun fact: Did try on 20.04 as the release notes stipulate,
but could not get Libero to load the required IPs to complete the assembly stage.