I2C bus speed BeagleV fire

BeagleV
1

Hi!
I am trying to set the I2C0 bus at a speed lower than 100kHz, but I always measure it at 156.25kHz. Just like explained here:
https://forum.microchip.com/s/topic/a5C3l000000Mee0EAC/t386291
From the gateware repo, I have tried changing it with a devicetree overlay.
I also so tried changing the MSS_*CLK_DIV factors in the MSS_configuration.cfg file, to lower the frequency of the clock generating the I2C SCL.
None of this seems to be applied to the gateware I build I and I still get 156.25kHz on the signal coming out of the cape pin.

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2

Just to make sure; did your design version change as you loaded the new build?

image
image887×628 33.2 KB

It’s a common “gotcha” to forget bumping the design version
and then spending hours pondering why your changes didn’t take…

3

Thanks for the answer!
I think you made me realize that updating the gateware from the ‘/usr/share/beagleboard/gateware/change-gateware.sh’ file does not apply the changes in the MSS_configuration.cfg file. It seems like I need to get a flashpro for this.

4

Depends on how you change the settings in your mss_configuration.cfg.

If you open it inside of Libero, the thing is read-only, but it can be opened with
the standalone tool, which then makes it read-write.

If you do it right, a flashpro should not be needed; your assumption is wrong.

I haven’t been playing with I2C per se, but it sounds odd that you should have
to change clock frequencies in the MSS. I would have thought it had prescaler registers.

In any case, please be advised that there’s a reason the MSS config is protected;
it’s very easy to make a bad bitstream this way and you could end up with an unresponsive BVF.

5

Hi! I have some news regarding this subject.
I indeed had an issue similar to what @lranders was referring to, although unfortunately not the exact same.
The Design Version was correct but the eNVM digest was not changing at each compilation.
This shows that the mpfs_bistream.spi did was not updated with the latest eNVM component and meant that I was deploying the same HSS over and over again.
A quick fix that I found for this was deleting the work directory before running the build_gateware.py file.
Doing so, I was able to lower the internal APB frequency down to 75MHz, which meant that the I2C frequency could not be set to lower values by the driver.
On top of this, I also had to modify the desired I2C frequency using a device tree overlay. Asking for 50kHz throught the dtso I measured 77kHz out of I2C_0.

@lranders, the reason why I thought I needed a Flashpro was because I was also confused by the name of the mpfs_bistream.spi file which contains more that just the fabric bitstream.
Thanks for your help!

6

I’m not sure if was clear enough on the bumping explanation…
In the screenshot I sent you, the design version is 1003.
Whenever you make a change, you increment this value by one, so 1004, 1005.
You really don’t need to delete your work directory every time, although it doesn’t hurt.

I will have to play with this some more, but it sounds very odd to me
that one needs to adjust the APB frequencies in the MSS configuration,
to change the I2C operating frequencies.

I suspect there’s still something amiss with the device-tree; asking for 50kHz should yield 50kHz.

@Vauban, care to weigh in here?

1 Like
7

Any more insight into the bus speeds? Here is what I know:

PCLK = 150Mhz

  • PCLK_DIV_960: 150,000 kHz / 960 = 156.25 kHz

  • PCLK_DIV_256: 150,000 kHz / 256 = 585.9375 kHz

  • PCLK_DIV_224: 150,000 kHz / 224 = 669.6429 kHz

  • PCLK_DIV_192: 150,000 kHz / 192 = 781.25 kHz

  • PCLK_DIV_160: 150,000 kHz / 160 = 937.5 kHz

  • PCLK_DIV_120: 150,000 kHz / 120 = 1250 kHz

  • PCLK_DIV_60: 150,000 kHz / 60 = 2500 kHz

    BCLK_DIV_8 ?? How to use?

48 MHz gives a clean 400/800:

  • PCLK_DIV_120: 48,000 kHz / 120 = 400 kHz
  • PCLK_DIV_60: 48,000 kHz / 60 = 800 kHz

24Mhz get us a good 400 and a not terrible 93Khz:

  • PCLK_DIV_256: 24,000 kHz / 256 = 93.75 kHz
  • PCLK_DIV_224: 24,000 kHz / 224 = 107.1429 kHz
  • PCLK_DIV_120: 24,000 kHz / 120 = 200 kHz
  • PCLK_DIV_60: 24,000 kHz / 60 = 400 kHz

The slowest we can go is 156Khz which is not great. I don’t really understand the BCLK option or if the BeagleV-Fire supports it. My understanding is we can use some tools to change PCLK, but at first glance it looks complicated and I was having a hard time locating documentation and tools to do it. Not sure if we can do it without affecting anything else (other clocks/other peripherals). Anybody have a tutorial written in crayons for people like me? :sweat_smile:

Thanks,
J

8

While it is possible to change the MSS setup itself (hereunder PCLK),
it’s also possible to get yourself into an unrecoverable situation,
where you could actually damage your Beagle, which is why it isn’t recommended.

The better alternate is to plug in another I2C IP on the fabric itself.
That way you have total control over your bit-rate.

All that being said, I do agree that Microchip could have done a better job
with the clock prescalers; they run out of bits rather quickly.
(the SDCARD speed issue comes to mind here)

Unfortunately, lowering PCLK will also make the APB a lot slower,
but perhaps that’s more of an issue in my head as opposed to real life.

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9

Hello,
Thanks for the feedback. I share your conclusions that changing the PCLK is not ideal. The issue I had was that the IC I was trying to communicate to in I2C needed a longer delay between the ACK and the data. Since I did not find a software option to control such a delay, I chose to lower the I2C clock down to 10kHz, which solved my issue.
In order to do this, I set the Baud rate clock to “Fabric I/O” which enabled the BLCK input on the MSS. I wired this input with a 10kHz clock signal generated by dividing by 5000 a 50MHz clock from a CCC PLL.

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10

Uuuu! I didn’t know that was an option! Thanks for sharing! :heart:

11

I see in the MSS Configurator how to connect B-CLK to fabric i/o. How did you connect your clock to the bclk input of the hard IP block? Could you give some more detail?

Thank you,
J

12

I added a module to divide the 50MHz FIC3 by 5000 in CLOCK_AND_RESETS and then connected this 10kHz clock (I2C_0_BLCK) to the BVF_RISCV_SUBSYSTEM:
sd_connect_pins -sd_name ${sd_name} -pin_names {“BVF_RISCV_SUBSYSTEM:I2C_0_BCLK_F2M” “CLOCKS_AND_RESETS:I2C_0_BCLK” }

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