Hi everyone,
i’m working on implementing RGMII1 of the CPSW9G switch using custom hardware.
The hardware design uses a DP83867 phy, just like BB-AI64 itself.
My initial idea was to setup the port via fixed-link, as the MDIO0 pins are routed to LEDs on the Beaglebone. For reference I used this TI overlay. I modified k3-j721e-beagleboneai64.dts and k3-j721e-main.dtsi as seen in the provided snippets. I have only provided my changes in the two files and omitted everything kept default.
The phy strap pins are kept at default values, except for its address pins.
Behaviour with this approach:
- Linux correctly identifies new interface and allows configuring
- Link is discovered by connected pc (auto negotiation works as intended)
- No dmesg errors regarding RGMII
- Ping in both directions fails with checksum errors
Other troubleshooting steps:
- Reducing speed to fast ethernet
- Using half-duplex
- Using different phy-modes
- Exported active DT to confirm that modifications are loaded
k3-j721e-main.dtsi
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw0_port1: port@1 {
status = "okay";
reg = <1>;
label = "port01";
phys = <&cpsw0_phy_gmii_sel 1>;
phy-mode = "rgmii-rxid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
k3-j721e-beagleboneai64.dts
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */
J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */
J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */
J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */
J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */
J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */
J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */
J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */
J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */
J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */
J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */
J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */
>;
};
&cpsw0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>;
};
Alternativ using MDIO:
I also tried using MDIO to test different rx/tx delays. But this required soldering wires to V26 and V24 and the phy was not discoverable over MDIO. With an oscilloscope I could measure traffic from the BB on the MDIO, without an answer from the phy. I’d like to remain using fixed-link, as I don’t have a need for configuring the phy and to prevent hardware modifications.
Does anyone have experience with the fixed-link ethernet approach? If more details are necessary for troubleshooting, let me know.