Increasing CLK SPEED

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1

Hi everyone,

Now that we already know our algorithm's running time, we are
preparing the optimization, this is, reducing that time.
Before dealing with assembler code, namely, trying to execute those
slowest function using .asm code instead of C code, I am trying to
increase the system frequency.

For me, I've seen at /arch/arm/mach-omap2/ clock_34xx.h that at
initialization the system sets a osc_ck =19,2 MHz and sys_ck=19,2 Mhz.

Since the structs and the functions that manage them are static and
can't overwrite the file, I have to fix these staff in my driver, but
I'm not sure.

I'd like to set up a osc_ck = 38,4 MHz and so for the sys_ck.

By the way: how can I see the values of the multipliers?. Remember I'm
trying to achieve the maximum speed for reducing my algorithm's
running time.

Hope I have been concise and clear, please help me.

Thanks

2

Now that we already know our algorithm's running time, we are
preparing the optimization, this is, reducing that time.
Before dealing with assembler code, namely, trying to execute those
slowest function using .asm code instead of C code, I am trying to
increase the system frequency.

Are you sure you reached the point where the only way for you
to get acceptable speed is to increase frequency? Are you
sure your algorithm is tuned well enough? That you are using
the right compiler with the right flags? And once this is done,
you can, as you wrote, turn to assembly language.

If after all of that you still need to overclock the chip, you should
start wondering if you chose the right platform for your needs :slight_smile:

Laurent

3

Obviously I must optimize the code by means of assembler code. The
fact is that if it exists the option to first increase the speed,
because the OMAP allows to... I'll be pleased and thank god.

It is the right platform, but first of all I'd like to see if at high
speed I win running time.

4

Obviously I must optimize the code by means of assembler code. The
fact is that if it exists the option to first increase the speed,
because the OMAP allows to... I'll be pleased and thank god.

It is the right platform, but first of all I'd like to see if at high
speed I win running time.

I'm not sure what you think you can achieve? What would you try to do?
Increate the speed from 500MHz to 600MHz? In order to get the 20% extra ARM
performance?

For rough calculations you will get the algorithm running ~20% faster during
this unless it's bound by external memory accesses, which might not run
faster even though you increase the speed of the ARM core itself. Is this
your goal?

Increasing the speed might however severely lower the chips life time (from
~11 to ~5 years according to the datasheet) - Both might however be high
enough not to cause any problems?...

But please state your overall goal/idea and it might be easier for people to
help you
- Currently I feel you are going down a wrong path...

Best regards
  Søren

5

Finally I managed to resolve the problem.

The BeagleBoard is set through an external crystal of 26 MHz.

This CLK and the external 32 KHz crystal comes into the OMAP 3530 once
passed through the TWL4030.

Inside the OMAP, I'm trying to manage the DPLL2: this is the DPLL
which manages the IVA2 subsystem.

If I make a directly read of the register, I obtain:

6

Finally I managed to find those registers I was looking for.

The OMAP 35300 is fed by two oscilators: 32kHz and 26MHz. These
signals pass through the TWL4030 and enter into the OMAP 3530.

I read the register which manages my IVA2 subsystem:

CM_FCLKEN_IVA2 = 0x00000001
CM_CLKEN_PLL_IVA2 = 0x00000037
CM_CLKSEL1_PLL_IVA2 =0x0009680C
CM_CLKSEL2_PLL_IVA2 = 0x00000001

Once read, I see that :

1. IVA2_CLK is enabled.
2. IVA2 internal frequency is set between 0.75 - 1 MHz.
3. The IVA2 DPLL automatic recalibration mode is disabled.
4. The IVA2 DPLL iin lock mode is enabled.

5. DPLL2_FCLK is CORE_CLK, which doesn't affects me because the lock
mode is enabled(and disabled the by-pass mode).
6. M (mult. factor) = 0x168 = 360.
7. N (div. facotr) = 12.
8. and the M2 diiver factor is 1.

So... what I'm trying to find out is the IVA2.2 Internal Clock.

I know that the IVA2.2 subsystem receives one single-clock signal
(DPLL2_ALWON_FCLK) from the PRCM.
From this clock (DPLL2_ALWON_FCLK) and by using the DPLL2 module in
the IVA2.2, three internal clocks are generated by the
IVA2.2 system control module (SYSC):

· CD0_CLK: Fastest IVA2.2 subsystem functional clock, dedicated to the
DSP. Its frequency can be adjusted at PRCM level by setting the
PRCM.CM_CLKSEL1_PLL_IVA2 and PRCM.CM_CLKSEL2_PLL_IVA2 registers.
· CD1_CLK: Divide-by-two of the CD0_CLK clock.
· CD2_CLK: Divide-by-two of the CD0_CLK clock.

As I trying to find out the frequency of the DSP once read my current
register values, I ask everyone if it exists a formula, as by example:

CLKOUT=( Fref x 2 x M)/ (N+1) which can answer me the running
frequency.

Hope I'm clear now !

In case I could increase the factor M, I'd achieve a frequency
increase which could be the KEY of my optimization before transforming
some functions in C code to ASM code.

THANKS.

7

Can you give us some hints about your algorithm? A few optimizing
people hang out here and can make some suggestions...

Have you tried oprofile to find the hot spots?

Do you understand ARM assembler and have you looked at the compiler
output for the critical routines?