Issue connecting SmartHLS AXI4 module to MSS via CoreAXI4Interconnect

BeagleV
1

Hi everyone,

I am currently working on a project using the BeagleV-Fire board and Libero SoC. I’m trying to create a simple adder module using SmartHLS and connect it to the MSS (RISC-V CPU) on the FPGA fabric.

  1. My SmartHLS Code I wrote a simple C code that adds two integers and successfully compiled it into a Verilog module using SmartHLS. Here is the source code:
#include <stdio.h>

void fpga_adder(int a, int b, int *sum) {
	#pragma HLS function top
	#pragma HLS interface argument(a) type(axi_target)
	#pragma HLS interface argument(b) type(axi_target)
	#pragma HLS interface argument(sum) type(axi_target) num_elements(1)

	*sum = a + b;

}

int main() {
	int res = 0;
	fpga_adder(10, 20, &res);
	printf("FPGA Adder Result: %d\n", res);
	return 0;
}
  1. Integration in Libero SoC After generating the Verilog and Tcl files, I cloned the official BeagleV-Fire gateware from the repository: git clone Making sure you're not a bot!

I executed the Tcl script to import my module into the BVF_RISCV_SUBSYSTEM. Since the PF_SOC_MSS’s FIC_0_AXI4_INITIATOR port was already in use, I tried to add a CoreAXI4Interconnect (v2.9.100) to arbitrate between the existing peripheral and my new adder module.
I made interconnector that has 1 master, 2 slaves pins.

  1. The Problem I configured the Interconnect and tried to make the connections, but I am facing a connection issue in SmartDesign:

MSS Side: FIC_0_AXI4_INITIATOR (Output from CPU) has 37 members.
Interconnect/Module Side: The connection point I’m trying to use seems to have 44 members.

Due to this mismatch in the number of members (37 vs 44), SmartDesign prevents me from connecting the MSS Initiator to the Interconnect (or the module). I suspect this is due to extra signals generated by SmartHLS or the Interconnect default settings.

I have tried adjusting the Interconnect configuration (1 Master/2 Slaves vs 2 Masters/1 Slave), but I haven’t been able to resolve the member mismatch error.

Could anyone advise on the correct CoreAXI4Interconnect configuration to bridge the PF_SOC_MSS (FIC_0) and a SmartHLS generated AXI4 Target? Specifically, how can I match the signal interface to the MSS’s 37-pin standard?

Any help or guidance would be greatly appreciated.

Thanks in advance!