Kernel PWM Logic

What is the logic behavior for Bullseye BBB and BBAI64 PWM’s. I know that I can’t change the /dev/bone/pwm/x/a or b pins period if a period for one of the pins has been previously set, and the OCP has been set to PWM for both pins. If only one of the a or b pins has been set, and the other OCP set to default I can change the period.

I am trying to write a PWM C++ class that traps this behavior.

BBB 5.10.145-ti-r55
BBAI64 5.10.153-ti-arm64-r86

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It appears to my testing that the logic used by the pwm pins associated with /dev/bone/x/a & b require the period for a & b to be the same. If for instance /dev/bone/x/a has been set the period for that pin can be changed provided the value for the shared pin /dev/bone/x/b is still set to 0 which is the default value on boot.