Limit mmc1 clock frequency

I have an actual Seeed Beaglebone Black Rev. C with kernel 4.19.94-ti-r42 #1buster SMP PREEMPT and u-boot U-Boot 2019.04-00002-g31a8ae0206.

To be more safe for a EMV test certificate I need to lower the internal MMC (mmc1) clock frequency and I am quite sure that this could be possible via device-tree[-overlay].

I found a success story at Limit mmc0 and mmc1 clock frequency with a quite similar setup but I am not shure which beagle-board is involved there. I also got a config snippet from Seeed support to do that which looks like an extension to DTO univ-bbb-Exx-00A0.dts so I created an own 12.dts file:

/ {
        fragment@0 {
                target = <&mmc1>;
                __overlay__ {
                        max-frequency = <25000000>;
                        /delete-property/ sd-uhs-sdr104;
                        /delete-property/ sd-uhs-sdr50;
                        /delete-property/ sd-uhs-ddr50;
                        /delete-property/ no-mmc-hs400;
                        /delete-property/ cap-mmc-highspeed;
                        /delete-property/ cap-sd-highspeed;

Compiled it an added it into the uEnv.txt


The log points out it get’s loaded

loading /boot/vmlinuz-4.19.94-ti-r42 ...
10095592 bytes read in 652 ms (14.8 MiB/s)
debug: [enable_uboot_overlays=1] ...
debug: [enable_uboot_cape_universal=1] ...
debug: [uboot_base_dtb_univ=am335x-boneblack-uboot-univ.dtb] ...
uboot_overlays: [uboot_base_dtb=am335x-boneblack-uboot-univ.dtb] ...
uboot_overlays: Switching too: dtb=am335x-boneblack-uboot-univ.dtb ...
loading /boot/dtbs/4.19.94-ti-r42/am335x-boneblack-uboot-univ.dtb ...
162266 bytes read in 40 ms (3.9 MiB/s)
uboot_overlays: [fdt_buffer=0x60000] ...
uboot_overlays: loading /lib/firmware/BB-ADC-00A0.dtbo ...
867 bytes read in 339 ms (2 KiB/s)
uboot_overlays: loading /lib/firmware/12.dtbo ...
226 bytes read in 202 ms (1000 Bytes/s)
uboot_overlays: loading /lib/firmware/BB-UART4-00A0.dtbo ...
1211 bytes read in 335 ms (2.9 KiB/s)
uboot_overlays: loading /lib/firmware/BB-BONE-eMMC1-01-00A0.dtbo ...
1741 bytes read in 301 ms (4.9 KiB/s)
uboot_overlays: loading /lib/firmware/BB-HDMI-TDA998x-00A0.dtbo ...
4915 bytes read in 311 ms (14.6 KiB/s)
uboot_overlays: loading /lib/firmware/AM335X-PRU-RPROC-4-19-TI-00A0.dtbo ...
3801 bytes read in 33 ms (112.3 KiB/s)
loading /boot/initrd.img-4.19.94-ti-r42 ...
6589689 bytes read in 429 ms (14.6 MiB/s)

But the clock speed of the mmc1 interface stucks at 48MHz (measured at pin 21 at P8).

What I wonder first is, why is linux considering running at 52MHz, while it actually runs at 48MHz?

root@yxcvbnm:/sys# cat ./kernel/debug/mmc1/ios
clock:          52000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    1 (mmc high-speed)
signal voltage: 0 (3.30 V)
driver type:    0 (driver type B)

Well, I admit, I won’t create this post if this worked. Should this work generally this way?
I extended also BB-BONE-eMMC1-01-00A0.dts and replaced the original file but as in the other thread I refer to, which is from year 2016, I have the strange feeling there is another mechanism taking over and the code running is completely something else…

Embedded MMC is not mmc1 in the device tree. It’s really confusing: the device tree’s MMCs indices start from 1, not 0. You must use mmc2.
Also, those lines are not needed:

                        /delete-property/ no-mmc-hs400;
                        /delete-property/ cap-mmc-highspeed;
                        /delete-property/ cap-sd-highspeed;

Thank you very much! :smiley:
It works! I removed those unnecessary lines also, compiled 12.dts to 12.dtbo and put it below /lib/firmware and this is sufficient!