Low-latency I/O RISC-V CPU core in FPGA fabric

I finally got my first edits to a gateware build up at https://openbeagle.org/jkridner/gateware. …and, I didn’t even change the Verilog, just worked on updating the device-tree overlay loaded with the gateware.

Usefully, I built the gateware from scratch and was able to install it using a Debian package and the change_gateware.sh script.

Check it out. Just blinks one of the on-board LEDs.

Also, found a Youtube video I haven’t yet watched. This developer went a bit further and used some custom Verilog for a fun LED effect. Note: I’ve also seen people building the SERV core using the OpenBeagle CI, so that might be a useful fork to explore.