On Fri, 26 Feb 2016 19:26:37 -0700, William Hermans
<yyrkoon@gmail.com> declaimed the following:
*I don't expect any response to this -- I think by now I'm rambling on*
* very vague hypothetical conditions...*
Well then, this post is a figment of your imagination 
Anyway, I don't
know much of PWM "theory", but just going by the file system attribute
names. Resolution is adjustable to the nanosecond, as is duty cycle. But at
any rate, a 2Mhz PWM would be fairly high. Especially considering that *a)*
this is a "freebie" on die module, and *b)* PWM functionality requires no
additional interaction from the main processor( but changing parameters
does, which is trivial / expected ).
Anyway, 1ns high, 1ns low. So whatever 2ns works out to.
If I haven't made mistakes, that would imply a 500MHz square wave...
Out of a module with, nominally, a 100MHz clock <G>
The confusion, I think, comes from the term "resolution". As I
understand the documentation, within a slower period PWM (in which it takes
multiple cycles of the PWM counter) the high resolution mode allows
adjusting the transition point at ns level. To be able to adjust the PWM
ratio by 1%, if the minimum adjustment is 1ns, implies the total period
100ns -> 10MHz.
The high resolution mode is still tied to the base clock for control of
the PWM period, and that is what I've not determined limits of... That is,
the TRM uses a 100MHz PWM clock in all examples (and mentions a pre-scaler
which can reduce the effective clock rate), but I don't see any
specifications on if that is a fixed value, or something that could be
different in implementation.
From the TI TRM:
The HRPWM is based on micro edge positioner (MEP) technology. MEP
logic is capable of positioning an
edge very finely by sub-dividing one coarse system clock of a
conventional PWM generator. The time step
accuracy is on the order of 150 ps. The HRPWM also has a self-check
software diagnostics mode to
check if the MEP logic is running optimally, under all operating
conditions.
I can't cut&paste table 15-38, but the row for 2MHz implies the regular
PWM effective resolution (meaning how finely can the transition be moved)
is now at 2% -- or 50 steps from full-off to full-on (if the PWM has those
end-points; I can envision still having a single tick on the period). The
high-resolution mode is capable of 0.036% adjustment in transition.
In high resolution mode, the MEP is not active for 100% of the PWM
period. It becomes operational
3 SYSCLK cycles after the period starts.
So there goes the low end... Tends to imply the minimum period that can
be handled in high-res mode is 3-6 cycles (but non-high-res is there --
three cycles probably gives duty cycle choice of 0%, 33%, 67%, 100%).
Table 15-40 gives, for a 100MHz system clock, a max of 5MHz for the PWM
and 10bit resolution in high res operation -- 56 MEP steps per clock.
But for the OP's enquiry... (getting back on topic)
I doubt if even 50MHz (half of the 100MHz clock) would be reliable, and
only as a 50% duty cycle square wave.
The PWM module is not meant to be a clock generator; it was meant for a
power or D/A conversion where lower frequencies are used to allow for
capacitor charging to some voltage level (or position control for servos,
and those run at really low periods, relatively speaking)
The PRUs run at 200MHz, don't they? A four-cycle loop holding an output
high for two cycles and low for the next two would produce a 50MHz square
wave. A two-cycle loop (I've not studied the op-codes, something like:
toggle-pin; branch PC-1) would support a 100MHz square wave. Three cycles
wouldn't produce a square wave, but a 33%/67% wave form, at around 66MHz?
52MHz is more in the realms of unmodulated radio carrier. That's a
stand-alone oscillator into which a lower (audio band) signal might be
mixed... The PWM might be used for generating a sidetone buzz, but
injecting a harmonic rich square wave into the mixer is not going to be
pleasant. Even morse code circuits put in a rise/fall time to avoid the
harmonics.
