more than two interrupts with a pru

I am trying to fire 5 interrupts from pru to host at different stages but only two interrupts are working.
Interrupts in pru code are defined from n=0 to 7 using
#define PRU_EVTOUT_n n+3

interrupts are generated with following line

MOV r31.b0, 32 | PRU_EVTOUT_n

on host c code they are read using following lines

prussdrv_pru_wait_event (PRU_EVTOUT_n);
prussdrv_pru_clear_event (PRU_EVTOUT_n, PRU1_ARM_INTERRUPT);

the above lines are working for n=0 and n=1 and not for 2<=n<=7.
I have tested on both the PRUs and the result is same, can anyone suggest me how many interrupts can fired from the PRUs at a given time so that the host c code is able to distinguish all of them.

I don’t remember exactly, but I don’t think there are more than 2 PRU-ARM interrupts on the PRUs. I believe the other interrupts can be mapped to system interrupts using the interrupt map that you pass to prussdrv_pruintc_init() (you’d have to write your own instead of using PRUSS_INTC_INITDATA). It’s been a while since I saw this, so maybe someone else should confirm this.

An alternative solution to your problem is use something like a interrupt vector, i.e., use part of the PRU RAM (maybe the first byte) to identify which interrupt happened. You’d send the interrupt as

; Set c24 and c25 (data RAM in PRU1 and PRU0)
LDI32 r0, 0x24020
LDI r1, 0
SBBO &r1, r0, 0, 4

SBCO r28, c24, 0, 4 ; Not sure about this line, you should check
MOV r31.b0, 32 | PRU_EVTOUT_0

and read it as

prussdrv_map_prumem(PRUSS0_PRU1_DATARAM, &pru1_mem); /* You might need to cast this to uint32_t */

prussdrv_pru_wait_event (PRU_EVTOUT_1);
prussdrv_pru_clear_event (PRU_EVTOUT_1, PRU1_ARM_INTERRUPT);

if(pru_mem1 == 0){
} else if (pru_mem1 == 1){
} …

This is sort of a sketch, no guarantees it will work out of the box! Still, hope it helps…

But according to the this link eight interrupts should be working right?

The PRU have 10 interrupts: 2 for the host and 8 that are exported to general ARM interrupts. You should check page 225 of the TRM. Host 0 and Host 1 (which are the low bits on the INTC0 register or something like that) are reserved for the PRUs to signal the ARM core. The other 8 can be attached to many different interrupts (64 with codes presented in Table 4.21 of the TRM).

I recall vaguely concluding that it wasn’t possible (or was too complicated) when I looked into that, but if you find a way it’s great. Still, you’ll have to rewrite the INTC initialization vector yourself to associate the appropriate interrupts to each channel and each channel to each host. If your application is not really sensitive to timing issues (i.e., if you can manage to stick a few more commands in there to control/check for the interrupts), I would not bother and would simply implement an interrupt vector.

well thank you and interrupt vector seems plausible way and I will have to try it with my case