Section 1.1.6.2.2 says “Maximum supported memory size: 256 MBytes”, but CS maximum size is 128 MBytes. Is the POP memory of the Beagle board using two CS?
If I want to interface 7x128MBytes of NAND with the CUS packages, do I need to use a lot of NAND chips on my board?
I agree, that the section 1.1.6.2.2 might be a bit misleading unless you really know how NAND flashes work internally. The NAND flashes are to be considered more like a storage medium, that as a “normal” NOR flash. You are i.e. not able to do XIP from NAND flashes as one might be used to from NOR flashes.
The NAND flash access is done through a special part of the GPMC dedicated to NAND flash access. Unlike the NOR case, the NAND flash isn’t controlled by a set of (multiplexed) address- and data-lines. It’s controlled by a set of 8 or 16 data-lines + a few control lines (see figure 1-3 in the document referred by you earlier) , on which both commands, addresses and data are send. (Kind of similar to the IDE interface of a Harddisk-drive in a PC – Very rough approximation though J)
A “typical” NAND flash consists of a set of pages (grouped in blocks) of size either 512 or 2048 bytes + 1/32 of the page size in a spare are (normally used for bad block handling and ECC for bit error handling). You access these pages by reading their content into memory and the deals with the data from there.
In your case, where you need to access 7x128MB, I would recommend you to change to a larger NAND device and only use one chip select – The OMAP supports NAND devices at least up to 8GB. In case you really need to access 7 different chips, you would need to use 7 chip selects on the CUS package…
For more info please refer to:
TRM (spruf98b.pdf) chapter 11 – Memory Sub- System
TRM (spruf98b.pdf) chapter 25.4.7.4 – ROM code NAND support