I'm looking to minimise current flow for a GPIO (input) but cannot
find this simple info in OMAP docs.
What is the highest resistance I should use for pulldown and pullup
resistors for a simple USER-switch-like GPIO switch detector? What is
the voltage threshold for a GPI to sample 1 versus 0?
eg. according to the SRM circuit diagram the USER switch GPIO pin has
a 10k pulldown but no pullup to Vdd. My app could have the switch
depressed for long period so I want to minimise current.
A switch change detection time of under 50ms is required.
I would not use an external resistor at all but instead use the internal pullups. The reason the user switch has a 10K pulldown is because the switch applies VDD when the switch is closed and there is no SW running before it is detected that would enable an internal pulldown. If you wnat to use an external pullup, a size of 47K should be OK. Remember, the IO voltage is 1.8V so the current will be low. As you have no capacitance, other than the amount created by any PCB capacitance due to the trace, there should be minimal delay in the line going low. As the GPIO has a relatively slow scan rate, I can’t see any delay of the line going to a low being of any significance.
In the case of the Angstrom kernel running, for a GPIO input, what is
the default internal pull direction? Pull-up or pull-down?
Can I change the pull direction via the sys/class/gpio interface if required?
Have a look at u-boot sources: board/beagle/beagleboard.h
there you will find PU/PD values unless you redefine them in Linux kernel with PIN_MUX
2010/8/10 Richard Andrews <email@example.com>
The kernel file
seems to setup the pin mux registers and hence the internal
Is there anywhere else?
This file works only if you enable it in the kernek config file. Usually it is omitted and u-boot settings work
2010/8/11 Richard Andrews <firstname.lastname@example.org>
OK. That's the piece of info I didn't understand.