Pass data to/from FPGA Verilog and RISC V Linux C

Can anyone point me in the direction of or provide any examples of how to exchange data between FPGA Verilog and a C program operating on the Linux system for the BeagleV fire. Even details of calling C functions from Verilog would be fine. Any advice would be much appreciated.

Think of the FPGA as a processor peripheral with memory mapped control and status registers. The Verilog code implements digital logic behind a set of control and status registers themselves implemented in Verilog. Software reads and writes the memory locations at which the control/status are exposed in the memory map to control the digital logic implemented using Verilog within the FPGA.
There are no function calls in C to Verilog or from Verilog to C on a deployed system. You may come across these types of function calls but they are related to digital logic verification test benches used to verify the correct operation of digital logic as part of a simulation.


Thanks Vauban. So is it possible to read from/write to these control/status registers or any utilise any shared memory between the FPGA logic and the Linux RISC V subsystem? My thinking is along the lines of reading a high speed ADC using the FPGA and storing that data in shared memory for processing by a higher level program deployed on the Ubuntu Linux system.

Hi @aloveday, I just uploaded a video where a C program running on a Linux RISC-V processor reads/writes to the FPGA Fabric/Gateware. I’m new to Linux programming (I usually run on bare metal), so this might not be the “right” way, but it’s working pretty good for me. Hope it helps. And I think you need to go to youtube if you want HD.

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@BustedWing1 This is very good!!! You have been busy.

Hi @aloveday , looks like @BustedWing1 provided a very good answer to your question regarding accessing FPGA control and status register. What you might consider for your high speed ADC is to either use a Memory FIFO in the FPGA where a state machine driving the ADC would write the sample results read from the ADC into the hardware FIFO and the software reads the samples from the memory mapped read port of the FIFO. This approach is fairly simple.
The second approach would be to have the same state machine driving the ADC in the FPGA and use DMA to write the samples into main DDR memory. This is a little more involved as you would probably want to have a small RAM buffer in the fabric to collect 16 ADC samples before generating an AXI burst to the memory for performance. With this approach the ADC samples magically appear in memory without the processor having to do the reads.

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Hi @BustedWing1 thank you for that. Exactly what I was looking for - that is certainly a great help and will set me off on the right path. I definitely appreciate the work that you have done in determining the base address of the cape and providing an example of how to do this. I’ll set up something similar to make sure I understand everything correctly. Hi @Vauban, yes I was thinking of starting with a FIFO and eventually progressing to using DMA - it’s all baby steps for me along the way of getting a good understanding of how everything works. I think this is a great little board for learning and ultimately building some useful solutions. I am very appreciative of the help and advice that both of you have provided.

YW, I’m happy to help. I’m just finding my way like you are and this forum, with folk like @Vauban, has been invaluable to me.

Glad you guys are having fun with this board.

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@BustedWing1 ,

Seth here. First off, I know too little to be of service. Secondly, I would like to know your name in so I can follow you and your current BeagleV-Fire read/write lesson…


P.S. I am signed into now and I searched the BeagleV-Fire sections but did no come across this build. Um, please send in your name so I can try it out!


Scratch what I said. I just found it.

Hi @silver2row
fyi, I broke my repo today. I’ve got it to compile again, but it doesn’t quite run right. I’ll try to fix it soon, but in the meantime, you may want to revert back to Monday’s build. And here’s the path to my repo. Busted Wing / Gateware-serv-on-fire · GitLab

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no issue…I need to set up the board and get things situated before handling the repo.

And A-Okay about the Monday repo build…

I will use it instead.


Hi Seth, my repo is working again. I added a little ram to the cape that the processors can read/write. I also added memwrite.c and memread.c to access the ram. I uploaded a video to my Youtube BeagleV-Fire playlist that shows how to use them.

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I have been using the BBB for a bit now. I am new to VHDL and Microchip FPGA PolarFire SoCs.

Anyway, I will test soon…

  1. I need to find out if updating and upgrading is available on the BeagleV-Fire first. I have a long way to go.
  2. Secondly, thank you for keeping the idea alive and working!


P.S. I need to get out my Ubuntu Distro with the FPGA Fabric programming interface and so on…(I think). New, I told 'ya.

It just works out of the box. I didn’t do any updating or upgrading. I didn’t make changes to Ubuntu. The gateware build procedure documentation is great: Customize BeagleV-Fire Cape Gateware Using Verilog — BeagleBoard Documentation

All you need is a USB-C cable (any maybe an ethernet cable). You do NOT need a special FlashPro programmer or JTAG. You do NOT need to install any software (the build is all done on BeagleBone servers).

I made a video about getting started with the gateware. It just followings the documentation but it may (or may not) be helpful. Good Luck

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I will test soon and report back!

Thank you for making me understand…



Dang! You and whomever else got to it! I did not know there was that much development for this board already. yes…

Another Update

Okay…so. Um, I think something was misconfigured. I cannot update/upgrade or use any networking behaviors so far. I cannot reach the outer world yet.

Hey Seth, I made this video on my first day with the Fire.
Out of the box it walks through using the USB commport, ssh over ethernet, and the Fire’s web server (also over ethernet). Can you get any of these to work?

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Not yet.

I can get on the board, sign in, get to u-boot, and learn about the eNVM.

Also, usb or mmc or sd does not boot for me (sort of). I can boot into what was delivered to me but the processor runs very-very-very hot-hot-hot. No issue so far. The board still runs as expected outside of WWW stuff.

I just tried a SD Card image but it is not loading so far. I am not quite sure how to go about producing a SD Card image that is bootable on the Fire.


For instance…

In the cli, I type mmc or sd and then after one of the two is when I type boot. Neither work in the cli.

When I get to u-boot, I can boot normally into the image that was provided by the distributor or whomever.


I got the UX up and running now and it seems that it is updating packages and services?


You’re way ahead of me on all of that stuff. I haven’t done anything with u-boot, eNVM or SD Cards. I just use Ethernet for scp to load new gateware images, and ssh to run the gateware build script.

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