[PATCH 0/6] ARM: Introduce function to switch to hypervisor mode and enable LPAE

BeagleBoard-X15
1

On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader.

Patch 1-4 enable LPAE.

Patch 5: Introduces a weak function which can be overridden specific to
SoCs to switch to hypervisor mode.

Patch 6: overrides weak function in patch 1 switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for hypervisor mode on OMAP5 based SoCs.

Tested on AM57XX-EVM, DRA7XX-EVM.

Keerthy (6):
  omap: Remove hardcoding of mmu section shift to 20
  omap: Set appropriate cache configuration for LPAE and non-LAPE cases
  configs: am57xx_evm_defconfig: Enable LPAE mode
  configs: dra7xx_evm_defconfig: Enable LPAE mode
  ARM: Introduce function to switch to hypervisor mode
  ARM: OMAP5+: Override switch_to_hypervisor function

arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 +++++++++++++++++++++
arch/arm/cpu/armv7/omap-common/omap-cache.c | 29 ++++++++++++++++++++++----
arch/arm/cpu/armv7/start.S | 21 +++++++++++++++++++
arch/arm/include/asm/system.h | 4 ++++
configs/am57xx_evm_defconfig | 1 +
configs/dra7xx_evm_defconfig | 1 +
6 files changed, 76 insertions(+), 4 deletions(-)

2

As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.

Signed-off-by: Keerthy <j-keerthy@ti.com>

3

Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.

In the case of LPAE the cache configuration happens via MAIR0 lookup.

Signed-off-by: Keerthy <j-keerthy@ti.com>

4

Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.

Signed-off-by: Keerthy <j-keerthy@ti.com>

5

Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.

Signed-off-by: Keerthy <j-keerthy@ti.com>

6

On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Signed-off-by: Keerthy <j-keerthy@ti.com>

7

Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.

Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.

Signed-off-by: Keerthy <j-keerthy@ti.com>

8

Reviewed-by: Tom Rini <trini@konsulko.com>

9

Reviewed-by: Tom Rini <trini@konsulko.com>

10

Reviewed-by: Tom Rini <trini@konsulko.com>

11

Reviewed-by: Tom Rini <trini@konsulko.com>

12

Reviewed-by: Tom Rini <trini@konsulko.com>

13

Reviewed-by: Tom Rini <trini@konsulko.com>

14

On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader.

Patch 1-4 enable LPAE.

Patch 5: Introduces a weak function which can be overridden specific to
SoCs to switch to hypervisor mode.

Patch 6: overrides weak function in patch 1 switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for hypervisor mode on OMAP5 based SoCs.

Tested on AM57XX-EVM, DRA7XX-EVM.

Tom,

Can you pull this series please.

Regards,
Keerthy

15

Applied to u-boot/master, thanks!

16

Applied to u-boot/master, thanks!

17

Applied to u-boot/master, thanks!

18

Applied to u-boot/master, thanks!

19

Applied to u-boot/master, thanks!

20

Applied to u-boot/master, thanks!