polarfire-soc-linux-examples DMA test on beagleV-Fire

BeagleV
1

I am trying to run the DMA example in the polarfire-soc-linux-examples github repository.

I have replicated the design as a separate component in the gateware, which can be found on my fork.

Based on the design, I’ve added the FPGA LSRAM, FPGA DMA Controller and some reserved memory in the device-tree overlay for this example, which can be found here.

I have succesfully compiled the design and loaded it onto the board but when running the example, I encounter a CPU stall.

beagle@BeagleV:~/polarfire-soc-linux-examples/dma$ sudo ./uio-dma-interrupt 
[sudo] password for beagle: 
locating device for dma-controller@60010000
located /dev/uio1
opened /dev/uio1 (r,w)
mapped 0x1000 bytes for /dev/uio1
locating device for fpga_lsram
located /dev/uio0
opened /dev/uio0 (r,w)
mapped 0x1000 bytes for /dev/uio0
mmap at c8000000 successful

         # Choose one of  the following options: 
         Enter 1 to perform memory test on LSRAM 
         Enter 2 to write data from LSRAM to LPDD4 via DMA access  
         Enter 3 to Exit
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Writing incremental pattern starting from address 60000000

Reading data starting from address 60000000 

Comparing data 

[  700.074384] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[  700.080340] rcu:     1-...0: (3 ticks this GP) idle=015c/1/0x4000000000000000 softirq=3964/3966 fqs=1989

Why is this stall being triggered? Is there anything wrong in the design? Is there anything wrong in the device-tree overlay? Any pointers will be appreciated.

1 Like
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An update to trying this example:

I was able to get LSRAM read and write working (thanks to @lranders for the help) by setting the AWID on the FIC0 Initiator to 8 and ID Width to 9 on the LSRAM module. This resulted in both having AWID as [8:0] vectors. FIC0 should specify that the ID Width setting leads to the actual wire being one element longer, or else this is a bug which should be fixed.

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Hello! I’m very interested in this topic, I’m trying to accelerate a color space conversion using the FPGA on BeagleV-Fire. After implementing the conversion in Verilog as a new option for CAPE gateware and communicating with the processor using the APB interface, I thought I could reduce more the processor time by using a DMA controller to manage memory access of the FPGA to the image stored, and after finishing the conversion, the DMA should send an interrupt to the processor. But I don’t really understand the steps of implementing this DMA controller. Do you have any documentation that you used for your project or any explanations for the source code in your repository?

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Judging from your topic-name, you’ve found Microchip’s own github repository.

That is possibly the reference right now, unless you want to ask Copilot…