I have had problems with beaglebone blacks simply not booting when power is applied, and I isolated the problem to two GPIO pins that sample a open drain outputs of other circuits which could be high when the system starts up. Is this a known feature, where all GPIO pins cannot have voltage applied to them until after the system boots? If that’s the case, how should I interface with these normally high outputs? Even if I put tri-state buffers on the inputs, I’m not sure I could guarantee that the power sequencing will safely avoid this situation. Is anyone familiar with this issue and does anyone have any suggestions?
Are the GPIO pins in question some of the bootstrap pins ? It could be you are changing the boot mode.
However it is generally not good to have power on any i/o pin of the processor before its main power rail is stable as you can potentially be powering parts of the chip. This goes for all micros not just the BBB.
I understand this - my question is how people suggest handling this type of power sequencing problem. If I can’t guarantee that these pins will be in a low state when the system boots, then I need to isolate them in some way. But I will check if these are related to the boot mode, in which case I may be able to move to a safer choice of GPIO pins. That sounds like a reasonable explanation. Thanks!
Indeed, I was using pins 45,46 on P8 which are latched as the boot configuration on reset and I suspect the power sequencing was causing this failure mode. I can gate these signals with a 74LVC1T45 enabled by the RESET_n output. This type of issue is addressed in similar ways in the BBB schematics.