Hey James!
Thanks for taking the time to help. I actually found my mistake in the overlay yesterday. Apparently, when you declare the mode and configuration for each pin in the &33xx_pinmux { ... block there is a third argument for each pin. From what I can tell, this third argument is a bitmask. In my overlay I set this mask to 0x00 (see the final overlay).
/dts-v1/;
/plugin/;
&{/chosen} {
overlays {
LowerCape_Rev1 = “2026-05-13”; /* Set the date this overlay was created */
};
};
&am33xx_pinmux {
lower_cape_rev1_chip0: lower-cape-rev1-chip0 {
pinctrl-single,pins = <
0x002c 0x27 0x00 /* Set P8.17 as in/out gpio0_27, Mode 7, Internal Pulldown Resistor Enabled /
0x01b4 0x27 0x00 / Set P9.41A as in/out gpio0_20, Mode 7, Internal Pulldown Resistor Enabled /
0x0028 0x27 0x00 / Set P8.14 as in/out gpio0_26, Mode 7, Internal Pulldown Resistor Enabled */
>;
};
lower_cape_rev1_chip1: lower-cape-rev1-chip1 {
pinctrl-single,pins = <
0x0034 0x27 0x00 /* Set P8.11 as in/out gpio1_13, Mode 7, Internal Pulldown Resistor Enabled */
0x0030 0x27 0x00 /* Set P8.12 as in/out gpio1_12, Mode 7, Internal Pulldown Resistor Enabled */
0x003c 0x27 0x00 /* Set P8.15 as in/out gpio1_15, Mode 7, Internal Pulldown Resistor Enabled */
0x0038 0x27 0x00 /* Set P8.16 as in/out gpio1_14, Mode 7, Internal Pulldown Resistor Enabled */
0x007c 0x27 0x00 /* Set P8.26 as in/out gpio1_29, Mode 7, Internal Pulldown Resistor Enabled */
0x0044 0x27 0x00 /* Set P9.23 as in/out gpio1_17, Mode 7, Internal Pulldown Resistor Enabled */
>;
};
lower_cape_rev1_chip2: lower-cape-rev1-chip2 {
pinctrl-single,pins = <
0x0094 0x27 0x00 /* Set P8.8 as in/out gpio2_3, Mode 7, Internal Pulldown Resistor Enabled */
0x009c 0x27 0x00 /* Set P8.9 as in/out gpio2_5, Mode 7, Internal Pulldown Resistor Enabled */
0x0098 0x27 0x00 /* Set P8.10 as in/out gpio2_4, Mode 7, Internal Pulldown Resistor Enabled */
0x008c 0x27 0x00 /* Set P8.18 as in/out gpio2_1, Mode 7, Internal Pulldown Resistor Enabled */
>;
};
lower_cape_rev1_chip3: lower-cape-rev1-chip3 {
pinctrl-single,pins = <
0x01ac 0x27 0x00 /* Set P9.25 as in/out gpio3_21, Mode 7, Internal Pulldown Resistor Enabled */
0x01a4 0x27 0x00 /* Set P9.27 as in/out gpio3_19, Mode 7, Internal Pulldown Resistor Enabled */
0x0194 0x37 0x00 /* Set P9.29 as in/out gpio3_15, Mode 7, Internal Pullup Resistor Enabled /
0x0198 0x0f 0x00 /* Set P9.30 as in/out gpio3_16, Mode 7, Internal Pullup/Pulldown Disabled, Input Disabled */
0x0190 0x37 0x00 /* Set P9.31 as in/out gpio3_14, Mode 7, Internal Pullup Resistor Enabled */
>;
};
lower_cape_rev1_uart4: lower-cape-rev1-uart4 {
pinctrl-single,pins = <
0x0070 0x2e 0x00 /* Set P9.11 as UART4_RX, Mode 6, No internal pullup or pulldown */
0x0074 0x0e 0x00 /* Set P9.13 as UART4_TX, Mode 6, No internal Pullup or pulldown */
>;
};
lower_cape_rev1_uart1: lower-cape-rev1-uart1 {
pinctrl-single,pins = <
0x0180 0x28 0x00 /* Set P9.26 as UART1_RX, Mode 0, No internal pullup or pulldown */
0x0184 0x08 0x00 /* Set P9.24 as UART1_TX, Mode 0, No internal Pullup or pulldown */
>;
};
lower_cape_rev1_i2c2: lower-cape-rev1-i2c2 {
pinctrl-single,pins = <
0x017c 0x2b 0x00 /* Set P9.19 as I2C2_SCL, Mode 3, No internal pullup or pulldown */
0x0178 0x2b 0x00 /* Set P9.20 as I2C2_SDA, Mode 3, No internal Pullup or pulldown */
>;
};
};
&uart1 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_uart1>;
};
&uart4 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_uart4>;
};
&gpio0 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_chip0>;
};
&gpio1 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_chip1>;
};
&gpio2 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_chip2>;
};
&gpio3 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_chip3>;
};
&i2c2 {
status = “okay”;
pinctrl-names = “default”;
pinctrl-0 = <&lower_cape_rev1_i2c2>;
clock-frequency=<100000>;
};
I compiled the source overlay again using the device tree compiler copied it into /boot/dtbs/6.19.6-bone11 , added the overlay to /boot/uEnv.txt and finally rebooted using sudo reboot. All pins were set correctly and I was able to use the gpioget and gpioset commands.
It’s odd how for the beaglebone black kernel version I’m using I need to add this third bitmask in the pin declarations while on the Pocket Beagle 2 kernel I was using a month ago, having just the pad address offset and the pin mode value was all I needed ( I didn’t add the third 0x00 bitmask value in the PB2 overlay I made). I guess the developers didn’t see a need for the third bitmask so got rid of it in the PB2 kernels? Regardless, this overlay works now and and I can rest easy at night now 
.
As for how I got the address offsets and values, I referred to the BBB schematics (rev C3 because I couldn’t find rev D which is what my board is at) to figure out which ball on the AM335x chip the pins were connected to. Then I looked through the AM335x chip manual (AM335x Sitara™ Processors datasheet (Rev. L) -Table 4-2) to find the pin name associated with that ball. Finally I went to the AM335x Technical Reference Manual (Oct. 2011) Table 9.10 to find the offset for the pin name I found in the datasheet. Hopefully that all makes sense.
To find the second value (which I call the pin mode declaration value) I just remember that bits 0-2 set the mode (0-7), bit 3 either enables or disables pull resistors (0 for enabled, 1 for disabled), bit 4 sets the pull resistor configuration (1 for pullup, 0 for pulldown), bit 5 either enables or disables that pins internal receiver (1 enables the internal receiver, 0 disables it), and bit 6 sets the slew rate (0 for fast, 1 for slow).
Thanks again!
-DJL
