I see that the SRM[1] ([2] is easier to read) for the BBAI shows that some PRU pins appear at 2 of the P8/P9 header pins.
Is this really so?
–Mark
[1] https://github.com/beagleboard/beaglebone-ai/wiki/System-Reference-Manual#pru-icss2-pin-access [2] https://docs.google.com/spreadsheets/d/1dFSBVem86vAUD7MLXvqdS-N0Efi8_g_O1iTqzql8DAo/edit#gid=0
Can you highlight which ones? I didn’t think this was the case. Ultimately, I’ll just track it down with the schematics and pinmux tool.
If you could add comments on https://docs.google.com/spreadsheets/d/1fE-AsDZvJ-bBwzNBj1_sPDrutvEvsmARqFwvbw_HkrE/edit?usp=sharing, that would be the most direct for me.
A quick glance at the table in the SRM and then a quick glance at dev.ti.com/sysconfig for pr2_pru0_gpi2 seems to indicate there are 2 balls where it can come out (AD4 and F9):
So, yes, it is likely to be correct.
It’s not a problem. I’m just surprised to see several on the ICSS2 PRU0 pins are attached to the header in two places.