Ok, I have been reading through this again and there are certainly things that are not clear.
However as far as the mapping goes.
A region is a mapping from 32 bit to 48 bit space. So you can map up to 16 regions.
What is unclear here for me yet, is does each module that needs RAT have its own 16 region RAT module, or is the RAT module global to all cores that need RAT and the 16 regions are shared.
I am inclined to think that there is a RAT module for each core that needs RAT.
But it is confusing. If you look at the Processors View Memory Map section 2.5
it appears that the 32 bit address space is divided between the various cores.
But I think this is misleading. Taking the Main R5 cores for example. Each has its own ATCM and BTCM memory. That is 4 individual 32k memory banks. However table 2.5 only lists 1 ATCM and 1 BTCM. So at least in the case of the R5 cores, the 32 bit address must be local to the core. I therefore assume that each cores 32 bit address space is only local to that core. If that is the case then each core must have its own RAT module.
That makes the 16 region limit more acceptable.
For mapping, if you look at the J721E_registers3.pdf section 8 you will find the RAT register definitions.
There are 4 main registers ( x 16 regions) that control the mapping.
These are all 32 bit regisiters. The ‘_k’ refers to the region, so these registers are repeated 16 times,
RAT_CTRL_k : has an enable bit and 6 bits to represent the size to use for mapping. Where number of bits is 0 - 32. A value of 0 maps a single 32 bit address to a single 48 bit address. Otherwise the number of bits dictates the size of the region from 2 bytes upto 4G, not that you could use that full space.
RAT_BASE_k: This is the start of the 32 bit address you want to map into 48 bits. The bottom x bits here are 0, where x is the number of bits you specify in RAT_CTRL_k
RAT_TRANS_L_k: This is the bottom 32 bits of the 48 bit address you want to map to. As with RAT_BASE_k the bottom x bits must be 0
RAT_TRANS_U_k: The top 16 bits of the 48 bit address.
Now looking at the Processors View Memory Map you will see that the cores have RAT regions allocated in their address space. These spaces are where you will need to map the 48 bit space into.
If we take an Main R5 core for example. Its address map has 5 RAT regions of various sizes, with ARMSS_RAT_REGION4 being the largest at 2G from 0x80000000 to the top of the 32bit address space.
This is plenty of space and you could map all 16 regions into this space.
So if we take the GPIO registers, they are between 0x0000600000 and 0x00006310FF in 48 bit space.
To map this into the R5 address space you would need to use a RAT size of at least 13 bits 0x1 - 0x1FFF. This would extend beyond the GPIO registers so you would need to make sure you don’t access the undefined region.
So the RAT registers would need to be:
RAT_CTRL_k 0x8000000D - MSB is enable, bottom 6 bits the size.
So with this mapping, if the R5 core reads from 0x80000000 it is actually reading 0x0000600000.
You could map it somewhere else if you wish. For example 0x80002000 is valid (bottom 13 bits are 0) but 0x80000100 is not valid as it is not aligned to 8K
Do that make it any clearer ? This is my understanding of the RAT module.
I could be wrong here of course. It is a very complicated chip.