I encounter a caching issue with my application. I will describe what I want to do, how I planned to do it and what goes wrong:
By using the PRU on my BBB, I want to timestamp a periodic rising edge on one input pin in a nanosecond scale and signal it to a Linux Kernel module on the ARM.
To receive an interrupt in my kernel module, I bridged the pin with the rising edge to a second one (timer4 interrupt).
This interrupt fires a few microseconds after the event happened.
To read values from the PRU with best determinism and lowest latency, I allocated some DDR memory with dma_alloc_coherent() in my kernel module and handout the address via debugfs to the PRU.
The PRU is in endless loop:
wait for rising edge, read out the PRU cycle counter and write the cycle counter to the DDR memory address.
This works like a charm and I got the event’s cycle counter snapshot in my kernel module!
The kernel module interrupt is firing a few microseconds after the event and has some jitter I want to avoid.
So I decided it would be best to burst the actual cycle counter to a second ram address for a ten thousand times by the PRU so when the Kernel module reads this ddr location, It knows the difference from the event’s cycle counter and the cycle counter now.
This does not work!
Initially everything appered to be working. I was reading out for example:
event cycles: 1000
now cycles: 4300
But to test the “now cycles” counter, I added to the kernel module to read it thousand times in a loop. Guess what? It is thousand times the same.
I tried a few options. For example to write and read two alternating memaddresses for this “now counter” by kernel and pru but nothing gives the results I expected.
It seems like anyone caches the results…
Any help? So many thanks… I hope the problem can be understood.