Hello there,
I’m building a PRU application, to receive data from an ADC. This ADC has a left/right clock signal, which is a square wave signal with a duty cycle of roughly 50%. This signal is connected to an enhanced GPIO input pin. I want to make the PRU sleep (or some kind of inactive, in order to save power) while waiting for an edge on this signal. So I used the PRU command SLP 1 , and registers the GPIO for the input signal, in the wakeup enable (WAKEUP_EN) register, to make the PRU sleep between the edges of the signal.
My problem is: When the input signal in high, the PRU seems to instantly wakeup after SLP 1 is called. Is there a way I can make the SLP command only wake the PRU up on an edge, or edit the input signal to generate pulses on its edges? Maybe through the interrupt controller? The delay from an edge on the input signal to execution on PRU is critical, so I have to use the enhanced GPIOs.
I’m using the BeagleBone Black (AM335x 1GHz ARM® Cortex-A8), running Linux beaglebone 3.8.13-bone47.
I hope my question is clear enough, I’m quite new to this stuff.
Hello there,
I’m building a PRU application, to receive data from an ADC. This ADC has a left/right clock signal, which is a square wave signal with a duty cycle of roughly 50%. This signal is connected to an enhanced GPIO input pin. I want to make the PRU sleep (or some kind of inactive, in order to save power) while waiting for an edge on this signal. So I used the PRU command SLP 1 , and registers the GPIO for the input signal, in the wakeup enable (WAKEUP_EN) register, to make the PRU sleep between the edges of the signal.
My problem is: When the input signal in high, the PRU seems to instantly wakeup after SLP 1 is called. Is there a way I can make the SLP command only wake the PRU up on an edge, or edit the input signal to generate pulses on its edges? Maybe through the interrupt controller? The delay from an edge on the input signal to execution on PRU is critical, so I have to use the enhanced GPIOs.
You could use logic gates to generate a pulse for each edge of your left/right clock signal. The pulse width will be the propagation delay of the logic gate so you can choose the appropriate logic family to give you the pulse width that works for the PRU. There a lots of examples around if you Google “logic dual edge detection”. Here is an example of a XOR gate with hysteresis and a RC input.
http://www.onsemi.com/pub_link/Collateral/AND8408-D.PDF
Regards,
John