TheLoneJoker wrote, on 11/04/2010 06:50 PM:
I was following instructions from the following link:
On looking at the section "Run the u-boot commands to flash the NAND",
within the sequence of uboot commands entered there is "nandecc hw"
and "nandecc sw". What do these commands do and what is the difference
between "hw" and "sw" ?
ECC stands for Error Correction Code - to simplify it, for x bits of data, we generate y bit code- which allows us to correct one bit flipped OR detect (but not correct) upto two bit errors. the typical s/w implementation until sometime back has been - s/w algos in MTD layer - used in both u-boot and kernel, had one ecc stored for every 256byte of data. this means that for every data we read, s/w needs to crunch it to generate the ECC code, in omap3 h/w GPMC (the controller that talks to the NAND part), has it's own ECC generator - this generates ECC for 512bytes -
using "s/w ECC" as done by MTD, you can detect upto 2 bit errors and correct upto 1 bit per 256byte data
using "h/w ECC" as done by GPMC, you can detect upto 2 bit and correct upto 1 bit per 512byte data
s/w ECC both generation(during writes) and verification(during reads) requires intensive CPU operation - increases latencies.
h/w ECC in comparison just requires register read to collect the ECC data.
this ECC data is stored in the spare area (or in MTD terminology oob area) per page of NAND data - the amount of ECC data obviously is larger for s/w ecc in comparison to h/w ECC for a given page size of data.
Further bootrom in OMAP3 only understands h/w ECC with the ECC stored in a specific offset in spare area - so there is no option, but to use h/w ecc for x-loader. choice of ecc for u-boot and kernel now-a-days has been more to use h/w ecc for performance reasons..