Read LPDDR4 Mode Registers

BeagleV
1

I’m working with PolarFire® SoC (beaglev-fire board) using HSS v0.99.50 (2025.07 build), HAL v2.3.102, and DDR driver v0.4.024. I tried to add code to read LPDDR4 mode registers after DDR training but before general operation. My test function looks like this:

static uint32_t mss_ddr_mode_register_read(uint32_t mr_address)
{
DDRCFG->MC_BASE2.INIT_MRR_MODE.INIT_MRR_MODE = 0x01U; // CS0
DDRCFG->MC_BASE2.CFG_MRR.CFG_MRR = mr_address;
delay(DELAY_CYCLES_5_MICRO);
return DDRCFG->MC_BASE2.CFG_MRRI.CFG_MRRI;
}

void test_mrr(void)
{
uint32_t mr5_val = mss_ddr_mode_register_read(5); // Manufacturer ID
uint32_t mr8_val = mss_ddr_mode_register_read(8); // Density & I/O width

printf("MR5 = 0x%02X\n", mr5_val);
printf("MR8 = 0x%02X\n", mr8_val);

}

The problem: MR5 always returns 0x0C (decimal 12) instead of the expected JEDEC manufacturer ID (e.g. 0xEC for Samsung). MR8 also return 0x0C.

From what I understand, earlier releases didn’t support MRR in the MSS DDR controller, but newer bare-metal releases were supposed to add this feature. Has anyone successfully read LPDDR4 mode registers (MR5/MR8) on PolarFire SoC? Is there a known workaround or a specific API in HSS/HAL that should be used instead of direct register access?

Thanks in advance for any insights!

1 Like
2

Hi Skylar,

Welcome to the forum! Always good to see new faces.

While I wouldn’t rule it out completely, I can’t help thinking
this question would be better suited for a Microchip FAE.

We mostly help people get started with their new BeagleV-Fires here,
i.e. how to change gateware; you know, first steps.

Your question is certainly interesting, but I think you’re a little past that… :wink:

3

What I would probably do as a first step though, would be to study
the memory training code in HSS to see if any insights could be gleaned that way.

That’s your very non-FAE answer, hehe…

4

Thanks for the suggestion!
I actually did study the memory training code in HSS to see if there were any clues about how MRR might be handled. Unfortunately, I wasn’t able to find a suitable answer or clear path forward there. The code gave me some context, but it didn’t explain why MR5 always returns 0x0C instead of the expected JEDEC ID.

I’m still trying to figure out if this is a hardware limitation of the MSS DDR controller or if there’s a specific HAL/HSS API I should be using instead of direct register access.