Hi Robert,
Thanks for the link. I had started to implement something similar myself (having first checked the mainline kernel), but hadn’t got the additional pinctrl working.
Although the device tree changes are work (reset pin assertion can be seen at kernel startup time with an oscilloscope), I haven’t yet found a way to trigger it from user space (tried mii-tool --reset eth0 and also ethtool --reset eth0 phy).
Also, I think the delay in that git commit is insufficient - having tested with the scope, when reset-delay-us = <2>; the capacitor C174 is only discharged a small amount (typically by about 0.3v, so that it only reaches about 3v) so the voltage on the reset pin doesn’t approach the threshold for a reset.
TLDR: to be conservative, I think it should be:
reset-delay-us = <280>;
How I arrived at that is as-follows:
By experimentation, the minimum time period that the GPIO can be negative so that the reset pin gets down to 0.64v (datasheet table 5-3 “Vilt” (min)) seems to be 140 µs (that is the time from when the voltage starts to fall until the time it reaches 0.64v). Maybe apply a safety-factor of 2x to account for component tolerances, which would give 280 µs.
The minimum assertion time for the RST pin is 100 µs (Table 5-7 “Trstia” (min)), but I think that can be ignored because the combination of C174 and R33 means that it takes several hundred µs for the voltage to subsequently rise above 0.81 v (Table 5-3 “Viht” (min)). If the value of C174 was reduced (or changed to “do not place”) in the future, then Trstia (min) would still be satisfied (280 µs > 100 µs).
Cheers,
Tim.