The convergence of software-defined radio (SDR) technology with the flexible muscle of BeagleBone’s RISC-V processors and the raw horsepower of FPGA’s parallel processing presents a thrilling landscape for innovation.
By leveraging the open-source nature of RISC-V, we can craft tailored hardware accelerators to integrate with Pothos, etc.
It’s really convenient that these controllers are integrated, so we don’t have to buy additional hardware to control or interface with new peripherals.
Goal: SDR toolkit integration with Beaglebone
Hardware Skills: Verilog, verification, FPGA, RF
Software Skills: Linux, C++,
Possible Mentors: @jkridner
Expected size of Projects: 175
Rating: Medium
Upstream Repository: TBD
Reference: TBD