I have to read and write the SRAM using an strange setting.
During two or four MCSPI words, I have to have the CS deactivated
between words (which in my case are 8-bit words) and the re-activate
it again, namely, change its state between active/inactive.
The manual SPIM_CSX assertion bit of the MCSPIm-CHxCONF register( 20th
bit) makes it possible as long as you have activated the SINGLE forced
channel bit (filed 0 of MCSPI_MODULCTRL, and thus being able to drive
the chip-select by the MCSPI_CHxCONF[] FORCE bit.
My problem seems to don't have the CS triggering between 4/2 spi-
words, however I have a pretty CLK signal and I can send data or read
data from the line.
And it scares me... because if there's not CS signal... how is
possible to manage other devices.
By the way, CS signal control is achived via Software, not
automatically but by using the 20th bit of the MCSPI_CHxCONF register.
Can anyone help me on this stuff?
thanks in advance