Hello! I’m designing a SYZYGY pod for the BeagleV-Fire. I’m implementing a 1000 Mbps ethernet PHY on the board, converting RJ45 signals (1000 BASE-T twisted pair from the ethernet cable) to RGMII out of the PHY chip. The RGMII signals will go through the SYZYGY connector and into the FPGA/SoC PolarFire.
I’m looking at the timing requirements of RGMII signalling and noted that the SYZYGY spec (Appendix A, page 28) suggests that SYZYGY Carriers (The BeagleV-Fire board in this case) should specify tolerances for interoperability.
The documentation for a SYZYGY device should include a table which outlines the compatibility and interoperability with other SYZYGY devices
and in the their example they show a table including a “Length Matching” Row.
I checked for any documentation in the design docs on the SYZYGY connector trace length matching: https://docs.beagleboard.org/latest/beaglev-fire.pdf but couldn’t find anything.
Is there any documentation on the trace distances from the SYZYGY connector to the SoC? Or is it known what kind of skew exists between pins of the SYZYGY on the BeagleV-Fire?
As a small aside, does anyone know if there are kicad files for the BeagleV-Fire board? I see there is a .brd file in the git repo.
Thank so much,
Eric