Technical Reference Manual for bbai64

General Discussion
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Hi Community,

I’m trying to track down the appropriate TI TRM for bbai64. I’m currently using these as reference:

(SPRUIM2H) AM64x /AM243x Processors Silicon Revision 2.0

(SPRUIL1C) J721E DRA829/TDA4VM Processors Silicon Revision 1.1

But the j721e doc is missing PRU ICSGG chapter/sections and I’ve confused what exactly the chip is on the bbai64.

I’m looking for the full pinmux options, ball number, and registers so I can adapt the device-tree and pinmux for my own applications.

Over the years I’ve been using BBB with PRUs for my academic research: GitHub - jonreal/openWearable

I have mostly successfully ported my project (openWearable) to bbai64 on ICSGG0, but want more control over pinmuxing. Here is the bbai64 branch, which is a work in progress: GitHub - jonreal/openWearable at am64x

I have found a table of pinmux for bbai64 on this forum, but I’m interested in how this table was put together, eg which TI TRMs include the information.

Thanks,

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Here’s my current overlay setup for reference: https://github.com/kevinacahalan/BeagleBoneAI64_Heterogeneous_App_Example/blob/master/custom_overlays/our-custom-bbai64-overlay.dtso

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This guy has some PRU examples

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Thanks for the great collection of resources.

I’m still confused why the TRM doesn’t have a PRU section. To be clear, I can use the PRUs on my board without issue but wanted the technical reference as a guide.

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I figure that table was put together with a mix of looking at the TDA4VM datasheet SoC pad tables, and matching those pad numbers with their corresponding BB pins as seen here: https://docs.beagleboard.org/boards/beaglebone/ai-64/03-design-and-specifications.html#p8-cape-header.

So for example, you can see that SoC pad AH21 maps to BB pin P8_03. From looking at the TDA4VM datasheet page 46 table 5-1, you can see that AH21 needs to be in mux mode 6 to be MCAN6_TX.

I have this walkthrough of custom pinmuxing that you may find helpful: https://github.com/kevinacahalan/BeagleBoneAI64_Heterogeneous_App_Example?tab=readme-ov-file#walkthrough-of-process-to-figure-out-muxing

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The PRUs are not officially supported for whatever dumb reason. Oddly there are some TI examples for them. https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/tree/examples/j721e

In the datasheet you see this, which is a lie…
image

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This was my main confusion. I see now where the SoC pads are in the data sheet including PRU capable pads. Thanks for your help – it’s exactly the answers I was looking for.

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