Hi, Y’all,
I’m thinking about building a fast simulation environment for BeagleBoard. Since the ARM cortex a8 model is freely available at ovpworld.org [1], it could be extremely interesting to build a virtual simulation platform with TLM (Transaction-level Modeling [2]) and SystemC [3] (C++ plus some libraries for system level design). Then a lot debugging (boot-loader, kernel, driver) can be done in the simulation environment without hardware. Does anyone have experience with this?
I know this is possible because I was working (in a course) with a simulation environment built this way for the TLL5000 learning board [4] (with a TLL5000 daughter board [5]). The processor model was borrowed from OpenOVP and only a couple of thousands of lines of C++ code were written as “wrappers” and “connectors” to bind the CPU and other devices (CPLD, USB controller, memory, FPGA, etc) together. Such simulation environment could benefit design/debugging of boot loaders, kernel, driver and even user-space applications.
I’m also interested in working in the JTAG project [6]. I know from reading mailing list and wiki [7] that the current OpenOCD only supports limited functionality and is only capable to debug non-cache and non-mmu applications so it wouldn’t work once kernel is loaded (thus can’t debug kernel or applications under Linux). However, I’m not sure this is mainly because such functionalities haven’t been implemented in OpenOCD or there are limits in the hardware itself that makes it currently impossible. Can anyone enlighten me on this?
Sincerely,
Hui
References:
[1] http://www.ovpworld.org/OVP_Open_Virtual_Platform/ARM-A8_CORTEX_models/
[2] http://en.wikipedia.org/wiki/Transaction-level_modeling
[3] http://en.wikipedia.org/wiki/SystemC
[4] http://129.116.230.50/TLL6219_User_Guide_Rev_3.0.pdf
[5] http://129.116.230.50/TLL5000_User_Guide_Ver1.3.pdf
[6] http://elinux.org/BeagleBoard/GSoC/Ideas#JTAG_debugging
[7] http://elinux.org/BeagleBoardOpenOCD
