Hi everyone. I am still quite need to the begealboneV and was hoping for some assistantance. So I sued the repo and minimal.ymal to generate the MSS and then added my own custom FPGA logic (wraped in a SD block and connected the exposed pins to the MSS) I am able to generate a the stream as a .spi but am struggling to create the device tree with my new logic included and am a bit confused by the demo. Hoping someone might be able to point me in the right direction for getting ym design onto the board!
Thanks
I’m guessing that what you’re saying is, you forked the repository here.
Once you push back your changes, the CI will run a build and you’ll find the output
by going to Build > Artifacts. Download, unpack the .zip file and use
scp, rsync or similar to copy the files to your beagle.
Once there, you can run
sudo change-gateware.sh <./artifacts/bitstreams/LinuxProgramming>
and it’ll rush off your new bitstream to the FPGA.
It’s normal that it takes about 10 secs for it to read and commit your new bits.
Just be patient and it’ll loop back to starting HSS and hopefully u-boot.
I couldn’t possibly comment on your device-tree; I have no clue what you changed…
I know, it’s always exciting to play around with new hardware,
but in your case, I think I’d experiment with running change-gateware.sh
on the bitstreams already available.
That way you could familiarize yourself with the process,
before heading into the deep end with your own design…
Thank you for the help! yes i did fork from the repository. I then added new logic in libero and am trying to create a new bitstream with the new logic via the build-bitsream. But I will defineitly work though the change-gateware with some of the existing designs. Thank you for the help