The BBB manual says both these things about applying inputs to the I/O
pins:-
NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES
HIGH.
Do not drive any external signals into the I/O pins until after
the VDD_3V3B rail is up.
So, do these actually mean basically the same thing, or if not, which
one is actually correct? Using the VDD_3V3B to gate external input is
much easier because of its greater current capability but both are
available on the headers so one could use either. (Or even worse, is
it *really* an AND requirement?)
When the BBB is powered down will these two signals go low early
enough so that input signals gated by them will be removed in time?
SYS_RESET is the safest way to do it as it is a signal that can be used with enough delay to allow the 3V3B to settle. The desired requirement is after the 3V3B is up. But that is not a nice signal to track as it is a voltage rail. Easy is not always the best way.
Power down is in the reverse order of power up. Once 3V3B is removed your circuitry should be powered down at that point.
Gerald
> The BBB manual says both these things about applying inputs to the I/O
> pins:-
>
> NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES
> HIGH.
>
> Do not drive any external signals into the I/O pins until after
> the VDD_3V3B rail is up.
>
>
> So, do these actually mean basically the same thing, or if not, which
> one is actually correct? Using the VDD_3V3B to gate external input is
> much easier because of its greater current capability but both are
> available on the headers so one could use either. (Or even worse, is
> it *really* an AND requirement?)
>
> When the BBB is powered down will these two signals go low early
> enough so that input signals gated by them will be removed in time?
>
SYS_RESET is the safest way to do it as it is a signal that can be used
with enough delay to allow the 3V3B to settle. The desired requirement is
after the 3V3B is up. But that is not a nice signal to track as it is a
voltage rail. Easy is not always the best way.
OK, it makes little odds really as there will be some sort of logic
driven by either SYS_RESET or 3V3B so the current drive will be minimal.
Power down is in the reverse order of power up. Once 3V3B is removed
your circuitry should be powered down at that point.
So if I used a device powered by the 3V3B to drive the ADC voltage input
(obviously potted down to a maximum of 1.8 volts) would that be safe
enough? E.g. an op-amp in follower mode?
OK, thanks for the very quick replies.