Why not use mipi-dsi 4 lanes?

Why not use mipi-dsi 4 lanes?

I am not very familiar with DSI displays.

What would the advantage of 4 lanes be?

The number of data lanes in the MIPI DSI interface physical link are unique but interchangeable (usually) data lines. The MIPI Alliance specifications do not specify a maximum resolution or frame rate .

It is up to you to negotiate and decide that with the display attached to your DSI host but a mismatch in the number of lanes needs to be resolved depending on the Display Controller in your SOC. Ofcourse, the maximum frame rate takes a hit if we use 2 lanes instead of 4.

Depending on the timing parameters specified in the LCD display datasheet, the maximum resolution and frame rate can be determined and it strongly depends on the Display Controller. Many high resolution display manufacturers prefer using 4 lanes so that the clock rate will not have to be ridiculously high to support a high frame rate