I have created a spreadsheet with the various pin mux options for the header pins.
I have included the datasheet page numbers for the relevant pin mux options as I would advise anyone using it to double check my entries.
I have coloured some of the cells by type to make viewing a bit easier.
Spreadsheet - Google Drive
If anyone spots any errors, could you please let me know - thanks
bbai64-pinmux.ods (21.6 KB)
Hello @benedict.hewson ,
Seth here. Thank you, sir. I really appreciate you putting forth effort in this matter. Just for reference here, I am highly unskilled, lazy, and full of testing.
So, on w/ the testing!
P.S. Hello Again, sorry. I see UART3 has, count 'em, three TX outputs. Is this for use on a co-processor or many co-processors?
Often on these large MPU’s many functions are available on multiple pins. This is probably to ease PCB layout and to keep pin count down.
I have not checked everything, but I believe every core has access to all peripherals on the chip. You need to check the datasheet - [DRA829/TDA4VM Technical Reference Manual on the TI website. Look at the system interconnect section.
This is fantastic, thanks very much for sharing it.
I have a similar spreadsheet I made a while back. So thank you for providing a means for me to cross check mine. I only found two problems with yours:
P8_38 AJ20 (data sheet pg 42) PRG1_PWM2_A1 is mode3, not mode2
P9_33 K24 (data sheet pg 20) MCU_ADC0_AIN0 should be MCU_ADC0_AIN4 (AIN0 is on K25)
Thanks for checking. I have updated the file on Google drive so the above link is fine.
Corrected pinmux spreadsheet.
bbai64-pinmux.ods (21.7 KB)