BBB RevD (and Industrial) IT66122 issues

[Konstantin]

Hi there,
we have problems connecting display to the new Rev D Beaglebone Black.
Well of course connecting is no problem, but some displays types display nothing at all.

We have a Waveshare 5 inch 800x480 display with a PCB attached to it offering HDMI input.
It has as interface IC a TI TFP401APZP.

This one works fine on Rev C BBBs and also very fine on our new Rev D BBBs.

We have another display of same format with a Lontium controller.

This one also works fine on Rev C BBBs and also very fine on our new Rev D BBBs.

Also we use a Raystar RJN05000H810YHDHU00 or Winstar WF50FTYFGDHNV.
Both are also 5 inch 800x480 with a PCB offering HDMI input and have a TI TFP401AI chip onto it.
They are looking identical.

Both work only with the old Rev C BBB, with the new Rev D BBB only black screen is displayed.
From system point of view it is connected HMDI wise.

First we thought we have trouble with the chip types on the PCBs attached to the Display converting the 40 Pin ribbon stuff format to HDMI, but the funny thing is: All 4 PCBs work, if we connect the working panel from the Wavesahre display to the other ones. So the “not working” is stuck to the panel alone. Or, so to say, the working Panel with the 40 key ribbon cable works on all PCBs.

The non working modules have some strange things needed to be done so their panels are displaying something, did somebody experience the same in a similair situation? What could it be the not working panels need to work? Aren’t they all the same?
The internet is full of LCD with such a connector and we have one not working…

Kind Regards!

[RobertCNelson]

@Konstantin

The non working modules have some strange things needed to be done so their panels are displaying something, did somebody experience the same in a similair situation? What could it be the not working panels need to work? Aren’t they all the same?

Sadly i have a view panels that don’t work on the new ITE6122 chipset the RevD uses, it’s going to take more testing/development on this new chipset to get to the state the original NXP TDA998x could handle.

Regards,

[Juan_Luis_Guerrero_F]

Hi Guys,

I need some help here. I am new to BeagleBone boards and Linux.

I bought a BB Black Industrial from DigiKey, so in theory, it is original.

I want to connect a monitor to it through the microHDMI, but the board does not recognise HDMI.

Since I do not have experience with Linux or the board, I asked ChatGPT for help, and I have been working for a long time trying to enable the HDMI output on my board without success.

The board I have comes with:
AM3358BZCZA100 processor.
IT66122FN/ 2510-CXS/ A1HH9A. (which I understand is the one that enables video output.)

I have tried:
dmesg | grep -i hdmi —> empty
i2cdetect -y 2 —> all lines with “–”
ls /sys/class/drm —> version

I have changed the Image, using:
AM335x 11.7 2023-09-02 4GB microSD IoT
AM335x 11.7 2023-09-02 4GB eMMC Xfce Flasher

But still not working with the HDMI output.

First and most important thing:

Can I really have HDMI output on the BB Black Industrial? If so, which Image should I use?

I really appreciate any help you can provide.

[Juan_Luis_Guerrero_F]

Hi Guys,

I need some help here. I am new to BeagleBone boards and Linux.

I bought a BB Black Industrial from DigiKey, so in theory, it is original.

I want to connect a monitor to it through the microHDMI, but the board does not recognise HDMI.

Since I do not have experience with Linux or the board, I asked ChatGPT for help, and I have been working for a long time trying to enable the HDMI output on my board without success.

The board I have comes with:
AM3358BZCZA100 processor.
IT66122FN/ 2510-CXS/ A1HH9A. (which I understand is the one that enables video output.)

I have tried:
dmesg | grep -i hdmi —> empty
i2cdetect -y 2 —> all lines with “–”
ls /sys/class/drm —> version

I have changed the Image, using:
AM335x 11.7 2023-09-02 4GB microSD IoT
AM335x 11.7 2023-09-02 4GB eMMC Xfce Flasher

But still not working with the HDMI output.

First and most important thing:

Can I really have HDMI output on the BB Black Industrial? If so, which Image should I use?

I really appreciate any help you can provide.

[RobertCNelson]

@Juan_Luis_Guerrero_F

I have changed the Image, using:
AM335x 11.7 2023-09-02 4GB microSD IoT
AM335x 11.7 2023-09-02 4GB eMMC Xfce Flasher

But still not working with the HDMI output.

You have a RevD, you need an image from 2025, with a 6.x based kernel to get HDMI

[Juan_Luis_Guerrero_F]

Hi Robert, thanks for your quick reply.

You are right, the board I have is a RevD.

I still have some doubts.
When I search in the Filter Software Distributions for the BeagleBone Black Industrial, none of them are based on kernel 6.x.

If I search for the “normal” BeagleBone Black, I see the last Image version are based on 6.x kernel, but the description confuse me, beacuse it says: “Debian IoT (non-graphical) image for BeagleBone Black based on TI am335x processor”,

So the non-graphical I understood was not able to have HDMI output. Is it that? If that is the case, any idea where can I download the Image based on 6.x kernel to have HDMI output?

Thanks a lot!

[RobertCNelson]

@Juan_Luis_Guerrero_F

So the non-graphical I understood was not able to have HDMI output. Is it that?

All those images have HDMI output enabled, just no windows manager installed by default.

[lranders]

I wonder if it’d be easier for @Juan_Luis_Guerrero_F to search through what is presently available in BB Imager?

[Harshkumar]

Hi Everyone,

LCD was working fine with BBB revC but as you know in RevD, HDMI chip is changed, the same display not working correctly.

To investigate need BBB RevD schematic to verify connection of AM335X with IT66122.

Link of working linux drivers for HDMI would be helpful as well.

Thanks.

[RobertCNelson]

Okay, just comping these threads into 1 as they all 3 have the same issue of the IT66122 not correctly detecting the HDMI panel..

One thing i haven’t personally tried yet is forcing the ‘edid’ value, in /boot/uEnv.txt: you’ll find a note:

#In the event of edid real failures, uncomment this next line:

cmdline=earlycon net.ifnames=0 video=HDMI-A-1:1024x768@60e

the ‘e’ should always force the panel to be on, and maybe forcing the timing make other panels work?

Please disable this line and report back:

for IT66122 device it using hte mainline IT66121 driver, which a custom drm_connector patch. Making sure you're not a bot!

Regards,

[Harshkumar]

Hi @RobertCNelson

Thanks for replay.

In my case display is working but just getting vertical purple line at left edge.
Questions:

1. How many data lines connected to IT66122 (16 or 24)?
2. Same question in other words, how IT66122 is configured? (24 bit mode or 12 bit DDR mode or something else)?
3. BBB RevD Schematic for IT66122 block will be helpful to understand connection.
4. Can you share Device tree settings for I2C, lcdc, and HDMI?

[RobertCNelson]

@Harshkumar

How many data lines connected to IT66122 (16 or 24)?

It’s wired for 16 bit just like original NXP framer..

Regards,

[Harshkumar]

okay thanks and what is bus width defined in dts??

[RobertCNelson]

I love how i have 24bit here… BeagleBoard-DeviceTrees/src/arm/ti/omap/am335x-boneblack-ite-hdmi.dtsi at v6.18.x · beagleboard/BeagleBoard-DeviceTrees · GitHub

i know something i’m going to test tonight..

ite,it66121.yaml « bridge « display « bindings « devicetree « Documentation -...

            properties:
              bus-width:
                description:
                  Endpoint bus width.
                enum:
                  - 12  # 12 data lines connected and dual-edge mode
                  - 24  # 24 data lines connected and single-edge mode
                default: 24

i sort of remember getting a 16bit patch from Seeed..

Regards

[Harshkumar]

@RobertCNelson
Thanks for replay..
Just curious how 24bit mode working with 16bit data lines??

Basically my display is 1024x600 so i tried 12 bit DDR mode but it is giving worst result than 24bit SDR.
I am planning to test 16bit YCbCr mode..

[RobertCNelson]

@Harshkumar

Just curious how 24bit mode working with 16bit data lines??

I think we are faking it.. this is a similar patch for BeaglePlay i think… by wiring a few things to gnd, we’ve converted 24bit 888 to 16 RGB: ti-linux-kernel-dev/patches/tiam62x/0001-HACK-drm-tidss-dt-property-to-force-16bit-VP-output-.patch at ti-linux-arm64-5.10.y · RobertCNelson/ti-linux-kernel-dev · GitHub

need to find my nda it66122 datasheet… but website shows; so it66121 → it66122 is the same

    Various video input interface supporting digital video standards such as: 
        - 24-bit RGB/YCbCr 4:4:4 with RB swap option
        - 16/20/24-bit YCbCr 4:2:2 with YC swap option
        - 8/10/12-bit YCbCr 4:2:2 (CCIR-656) 

[RobertCNelson]

Units i have:

Working: (old V196L)

voodoo@labdev:~$ cat /sys/class/drm/card0-HDMI-A-1/edid | parse-edid
Checksum Correct

Section "Monitor"
	Identifier "V196L"
	ModelName "V196L"
	VendorName "ACR"
	# Monitor Manufactured week 22 of 2014
	# EDID version 1.3
	# Digital Display
	DisplaySize 380 300
	Gamma 2.20
	Option "DPMS" "true"
	Horizsync 31-83
	VertRefresh 56-76
	# Maximum pixel clock is 170MHz
	#Not giving standard mode: 1152x864, 75Hz
	#Not giving standard mode: 1280x960, 60Hz
	Modeline 	"Mode 0" -hsync +vsync 
EndSection

voodoo@labdev:~$ dmesg | grep tilcd
[    3.549541] [drm:tilcdc_drm_init] init
[    3.767011] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    3.767050] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    3.767065] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    3.767078] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    3.773671]  drm_atomic_helper_shutdown from tilcdc_fini+0x35/0x80
[    3.773694]  tilcdc_fini from tilcdc_init.constprop.0+0x175/0x494
[    3.773709]  tilcdc_init.constprop.0 from tilcdc_pdev_probe+0x3b/0x78
[    3.773724]  tilcdc_pdev_probe from platform_probe+0x41/0x6c
[    3.775237] tilcdc 4830e000.lcdc: [drm] *ERROR* Disabling all crtc's during unload failed with -12
[    6.401425] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    6.401484] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    6.401506] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    6.401523] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    6.486653] [drm] Initialized tilcdc 1.0.0 for 4830e000.lcdc on minor 0
[    6.513405] tilcdc 4830e000.lcdc: [drm] Cannot find any crtc or sizes
[    6.526680] tilcdc 4830e000.lcdc: [drm] Cannot find any crtc or sizes
[    6.654762] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.654917] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@75 with pixel clock 108000
[    6.655031] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x960@60 with pixel clock 108000
[    6.655140] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    6.655251] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@56 with pixel clock 36000
[    6.655361] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@75 with pixel clock 31500
[    6.655471] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@73 with pixel clock 31500
[    6.655580] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@67 with pixel clock 30240
[    6.655606] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.655716] [drm:tilcdc_crtc_mode_valid] Processing mode 720x400@70 with pixel clock 28320
[    6.655826] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@75 with pixel clock 135000
[    6.655850] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.655957] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@75 with pixel clock 78750
[    6.656066] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@70 with pixel clock 75000
[    6.656176] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    6.656286] [drm:tilcdc_crtc_mode_valid] Processing mode 832x624@75 with pixel clock 57284
[    6.656396] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@75 with pixel clock 49500
[    6.656503] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@72 with pixel clock 50000
[    6.674028] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.674087] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.674150] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.674187] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    6.681978] [drm:tilcdc_crtc_set_mode] 1280x1024, hbp=248, hfp=48, hsw=112, vbp=38, vfp=1, vsw=3
[    6.682474] [drm:tilcdc_crtc_set_clk] lcd_clk=216000000, mode clock=108000, div=2
[    6.683473] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[    6.699750] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.699791] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    6.721093] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.721191] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    6.791896] tilcdc 4830e000.lcdc: [drm] fb0: tilcdcdrmfb frame buffer device
[    6.909930] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.910071] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x960@60 with pixel clock 108000
[    6.910184] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@75 with pixel clock 108000
[    6.910295] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@75 with pixel clock 78750
[    6.910406] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@70 with pixel clock 75000
[    6.910518] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    6.910627] [drm:tilcdc_crtc_mode_valid] Processing mode 832x624@75 with pixel clock 57284
[    6.910738] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@75 with pixel clock 49500
[    6.910846] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@72 with pixel clock 50000
[    6.910954] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    6.911064] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@56 with pixel clock 36000
[    6.911174] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@75 with pixel clock 31500
[    6.911284] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@73 with pixel clock 31500
[    6.911394] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@67 with pixel clock 30240
[    6.911420] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.911530] [drm:tilcdc_crtc_mode_valid] Processing mode 720x400@70 with pixel clock 28320
[    6.911640] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@75 with pixel clock 135000
[    6.911664] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.912082] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.912125] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   12.001246] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0
[   55.546700] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   55.546741] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   55.546783] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[   57.196227] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.196269] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.286016] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.286057] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.669010] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.669049] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.826102] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.826145] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   62.945243] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0

Units I’m testing:

Waveshare 4 Inch HDMI LCD Screen 800x480: Amazon.com: waveshare 4 inch HDMI LCD IPS Display 800x480 Resolution Resistive Touch Screen HDMI Interface for Raspberry Pi 4B/3B+/3B/2B/B+/A+/Zero W,Support Raspbian/Ubuntu/Kali/Retropie : Electronics (on order)

Waveshare 5 Inch HDMI LCD Screen 800x480: Amazon.com: Waveshare 5 Inch HDMI LCD Screen 800x480 TFT Capacitive Touch Screen Display Monitor for Raspberry Pi 4B/3B+/A+/B/2B/B+/A+/Zero W Compatible with Windows 10/8.1/8/7 : Electronics (on order)

Old Rev C

voodoo@labdev:~$ dmesg | grep tilcdc
[    3.548673] [drm:tilcdc_drm_init] init
[    5.827413] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    5.827472] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    5.827493] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    5.827510] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    5.828162] tilcdc 4830e000.lcdc: bound 0-0070 (ops tda998x_ops)
[    5.836228] [drm] Initialized tilcdc 1.0.0 for 4830e000.lcdc on minor 0
[    5.864891] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    5.865048] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@75 with pixel clock 108000
[    5.865163] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x960@60 with pixel clock 108000
[    5.865324] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    5.865440] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@56 with pixel clock 36000
[    5.865551] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@75 with pixel clock 31500
[    5.865661] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@73 with pixel clock 31500
[    5.865772] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@67 with pixel clock 30240
[    5.865798] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    5.865908] [drm:tilcdc_crtc_mode_valid] Processing mode 720x400@70 with pixel clock 28320
[    5.866018] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@75 with pixel clock 135000
[    5.866042] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    5.866149] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@75 with pixel clock 78750
[    5.866259] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@70 with pixel clock 75000
[    5.866369] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    5.866478] [drm:tilcdc_crtc_mode_valid] Processing mode 832x624@75 with pixel clock 57284
[    5.866588] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@75 with pixel clock 49500
[    5.866697] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@72 with pixel clock 50000
[    5.883817] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    5.883871] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    5.883928] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    5.883965] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    5.892957] [drm:tilcdc_crtc_set_mode] 1280x1024, hbp=248, hfp=48, hsw=112, vbp=38, vfp=1, vsw=3
[    5.893471] [drm:tilcdc_crtc_set_clk] lcd_clk=216000000, mode clock=108000, div=2
[    5.894227] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[    5.910634] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    5.910664] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    5.931712] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    5.931741] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    5.954441] tilcdc 4830e000.lcdc: [drm] fb0: tilcdcdrmfb frame buffer device
[    6.017689] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.017832] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x960@60 with pixel clock 108000
[    6.017944] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@75 with pixel clock 108000
[    6.018055] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@75 with pixel clock 78750
[    6.018165] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@70 with pixel clock 75000
[    6.018275] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    6.018385] [drm:tilcdc_crtc_mode_valid] Processing mode 832x624@75 with pixel clock 57284
[    6.018495] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@75 with pixel clock 49500
[    6.018603] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@72 with pixel clock 50000
[    6.018711] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    6.018820] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@56 with pixel clock 36000
[    6.018931] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@75 with pixel clock 31500
[    6.019042] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@73 with pixel clock 31500
[    6.019152] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@67 with pixel clock 30240
[    6.019178] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.019288] [drm:tilcdc_crtc_mode_valid] Processing mode 720x400@70 with pixel clock 28320
[    6.019398] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@75 with pixel clock 135000
[    6.019422] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.019834] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.019877] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   11.233297] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0
[   54.302364] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   54.302405] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   54.302447] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[   57.092116] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.092158] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.167282] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.167324] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.549552] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.549593] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.642626] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.642667] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   62.689285] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0

[RobertCNelson]

Laughs… this display doesn’t work with Rev C or Rev D… taking out of testing!!!

DFR0506: (not working)
link: https://www.digikey.com/en/products/detail/dfrobot/DFR0506/8019056

voodoo@labdev:~$ cat /sys/class/drm/card0-HDMI-A-1/edid | parse-edid
Checksum Correct

Section "Monitor"
	Identifier "LONTIUM"
	ModelName "LONTIUM"
	VendorName "LTM"
	# Monitor Manufactured week 46 of 2010
	# EDID version 1.3
	# Digital Display
	# Display Physical Size not given. Normal for projectors.
	Gamma 2.20
	Option "DPMS" "false"
	Horizsync 26-81
	VertRefresh 24-75
	# Maximum pixel clock is 230MHz
	#Not giving standard mode: 1280x720, 60Hz
	#Not giving standard mode: 1280x800, 60Hz
	#Not giving standard mode: 1280x1024, 60Hz
	#Not giving standard mode: 1440x900, 60Hz
	#Not giving standard mode: 1600x900, 60Hz
	#Not giving standard mode: 1600x1200, 60Hz
	#Not giving standard mode: 1920x1080, 60Hz

	#Extension block found. Parsing...
	Modeline 	"Mode 11" -hsync +vsync 
	Modeline 	"Mode 0" +hsync +vsync 
	Modeline 	"Mode 1" +hsync +vsync 
	Modeline 	"Mode 2" 74.250 1280 1390 1420 1650 720 725 730 750 +hsync +vsync
	Modeline 	"Mode 3" 74.250 1280 1720 1760 1980 720 725 730 750 +hsync +vsync
	Modeline 	"Mode 4" 25.200 640 656 752 800 480 490 492 525 -hsync -vsync
	Modeline 	"Mode 5" 27.027 720 736 798 858 480 489 495 525 -hsync -vsync
	Modeline 	"Mode 6" 27.027 720 736 798 858 480 489 495 525 -hsync -vsync
	Modeline 	"Mode 7" 27.000 720 732 796 864 576 581 586 625 -hsync -vsync
	Modeline 	"Mode 8" 27.000 720 732 796 864 576 581 586 625 -hsync -vsync
	Modeline 	"Mode 9" 148.500 1920 2448 2492 2640 1080 1084 1089 1125 +hsync +vsync
	Modeline 	"Mode 10" 148.500 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync
	Modeline 	"Mode 12" -hsync +vsync 
	Modeline 	"Mode 13" +hsync +vsync 
	Modeline 	"Mode 14" +hsync +vsync 
	Option "PreferredMode" "Mode 11"
EndSection

video=HDMI-A-1:1280x720@60e

[    6.368360] [drm] forcing HDMI-A-1 connector on
[    6.458359] [drm] Initialized tilcdc 1.0.0 for 4830e000.lcdc on minor 0
[    6.853511] tilcdc 4830e000.lcdc: [drm] fb0: tilcdcdrmfb frame buffer device
[   19.901860] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
[   22.624481] systemd[1]: modprobe@drm.service: Deactivated successfully.
[   22.650812] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.

adding drm.debug=0x1

Gives…

voodoo@labdev:~$ dmesg | grep tilcdc
[    3.550419] [drm:tilcdc_drm_init] init
[    3.767500] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    3.767539] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    3.767555] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    3.767568] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    3.773353]  drm_atomic_helper_shutdown from tilcdc_fini+0x35/0x80
[    3.773376]  tilcdc_fini from tilcdc_init.constprop.0+0x175/0x494
[    3.773392]  tilcdc_init.constprop.0 from tilcdc_pdev_probe+0x3b/0x78
[    3.773407]  tilcdc_pdev_probe from platform_probe+0x41/0x6c
[    3.774927] tilcdc 4830e000.lcdc: [drm] *ERROR* Disabling all crtc's during unload failed with -12
[    6.413150] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    6.413207] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    6.413228] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    6.413245] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    6.499066] [drm] Initialized tilcdc 1.0.0 for 4830e000.lcdc on minor 0
[    6.514549] tilcdc 4830e000.lcdc: [drm] Cannot find any crtc or sizes
[    6.537716] tilcdc 4830e000.lcdc: [drm] Cannot find any crtc or sizes
[    6.772636] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x600@60 with pixel clock 51250
[    6.772949] [drm:tilcdc_crtc_mode_valid] Processing mode 1360x768@60 with pixel clock 85500
[    6.773076] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x768@60 with pixel clock 79500
[    6.773189] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x800@60 with pixel clock 83500
[    6.773387] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    6.773498] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.773608] [drm:tilcdc_crtc_mode_valid] Processing mode 1440x900@60 with pixel clock 88750
[    6.773718] [drm:tilcdc_crtc_mode_valid] Processing mode 1600x900@60 with pixel clock 108000
[    6.773743] [drm:tilcdc_crtc_mode_valid] Pruning mode: exceeds defined bandwidth limit
[    6.773934] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1080@60 with pixel clock 148500
[    6.773958] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.774063] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    6.774090] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.774199] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    6.774309] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@75 with pixel clock 108000
[    6.774337] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    6.774373] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@50 with pixel clock 74250
[    6.774399] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.774425] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27000
[    6.774452] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27000
[    6.774487] [drm:tilcdc_crtc_mode_valid] Processing mode 720x576@50 with pixel clock 27000
[    6.774522] [drm:tilcdc_crtc_mode_valid] Processing mode 720x576@50 with pixel clock 27000
[    6.774565] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1080@50 with pixel clock 148500
[    6.774589] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.774620] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1080@60 with pixel clock 148500
[    6.774644] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.774672] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    6.774698] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    6.774725] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27027
[    6.774752] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27027
[    6.774785] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1080@60 with pixel clock 148352
[    6.774810] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.780061] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x600@60 with pixel clock 51250
[    6.780116] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x600@60 with pixel clock 51250
[    6.780181] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[    6.780218] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[    6.788280] [drm:tilcdc_crtc_set_mode] 1024x600, hbp=160, hfp=140, hsw=20, vbp=20, vfp=12, vsw=3
[    6.790136] [drm:tilcdc_crtc_set_clk] lcd_clk=102500000, mode clock=51250, div=2
[    6.791150] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[    6.807143] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[    6.807183] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[    6.826100] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[    6.826141] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[    6.913553] tilcdc 4830e000.lcdc: [drm] fb0: tilcdcdrmfb frame buffer device
[    7.096889] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x600@60 with pixel clock 51250
[    7.097131] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    7.097173] [drm:tilcdc_crtc_mode_valid] Processing mode 720x576@50 with pixel clock 27000
[    7.097210] [drm:tilcdc_crtc_mode_valid] Processing mode 720x576@50 with pixel clock 27000
[    7.097237] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27027
[    7.097265] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27027
[    7.097292] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27000
[    7.097318] [drm:tilcdc_crtc_mode_valid] Processing mode 720x480@60 with pixel clock 27000
[    7.097344] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    7.097371] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    7.097396] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    7.097887] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[    7.097929] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[   12.256858] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0
[   54.515185] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[   54.515227] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[   54.515267] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[   56.334413] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[   56.334454] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[   56.401859] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[   56.401901] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[   56.711704] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[   56.711746] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[   56.798801] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1344, vtotal 635, vdisplay 600
[   56.798878] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 51250 kHz framedur 16652487 linedur 26224
[   61.934849] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0

[RobertCNelson]

Okay i’m giving up for today… went thru 4 panels that didn’t even work on the Rev C, just not enough pixel clock…

Then found one that works on RevC, and … also on RevD..

Works on both: https://www.digikey.com/en/products/detail/dfrobot/DFR1170/26460582

voodoo@labdev:~$ cat /sys/class/drm/card0-HDMI-A-1/edid | parse-edid
Checksum Correct

Section "Monitor"
	Identifier "P105FC"
	ModelName "P105FC"
	VendorName "CYS"
	# Monitor Manufactured week 24 of 2024
	# EDID version 1.3
	# Digital Display
	DisplaySize 230 130
	Gamma 2.20
	Option "DPMS" "true"
	Horizsync 30-84
	VertRefresh 50-75
	# Maximum pixel clock is 200MHz
	#Not giving standard mode: 1152x864, 60Hz
	#Not giving standard mode: 1280x1024, 60Hz
	#Not giving standard mode: 1600x900, 60Hz
	#Not giving standard mode: 1920x1080, 60Hz
	#Not giving standard mode: 1280x720, 60Hz

	#Extension block found. Parsing...
#WARNING: I may have missed a mode (CEA mode 69)
#DOUBLE WARNING: It's your first mode, too, so this may actually be important.
	Modeline 	"Mode 2" -hsync -vsync 
	Modeline 	"Mode 0" +hsync +vsync 
	Modeline 	"Mode 1" 
	Option "PreferredMode" "Mode 2"
EndSection

voodoo@labdev:~$ dmesg | grep tilcd
[    3.551057] [drm:tilcdc_drm_init] init
[    5.823473] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    5.823532] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    5.823554] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    5.823572] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    5.824227] tilcdc 4830e000.lcdc: bound 0-0070 (ops tda998x_ops)
[    5.832278] [drm] Initialized tilcdc 1.0.0 for 4830e000.lcdc on minor 0
[    5.881967] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1280@60 with pixel clock 164000
[    5.882031] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    5.882141] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1080@60 with pixel clock 148500
[    5.882167] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    5.882274] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@60 with pixel clock 81579
[    5.882384] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    5.882495] [drm:tilcdc_crtc_mode_valid] Processing mode 1600x900@60 with pixel clock 108000
[    5.882519] [drm:tilcdc_crtc_mode_valid] Pruning mode: exceeds defined bandwidth limit
[    5.882543] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    5.882651] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    5.882678] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    5.882787] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    5.882851] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    5.882879] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    5.882905] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    5.882968] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    5.893153] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    5.893320] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    5.893385] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    5.893422] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    5.904612] [drm:tilcdc_crtc_set_mode] 1280x1024, hbp=248, hfp=48, hsw=112, vbp=38, vfp=1, vsw=3
[    5.905079] [drm:tilcdc_crtc_set_clk] lcd_clk=216000000, mode clock=108000, div=2
[    5.905994] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[    5.922219] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    5.922249] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    5.943345] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    5.943377] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    5.965914] tilcdc 4830e000.lcdc: [drm] fb0: tilcdcdrmfb frame buffer device
[    6.088329] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.088503] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@60 with pixel clock 81579
[    6.088536] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    6.088600] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    6.088627] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    6.088691] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    6.088801] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    6.088909] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    6.088936] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    6.088961] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.089546] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.089592] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   11.233304] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0
[   55.374247] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   55.374287] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   55.374327] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[   56.775331] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   56.775373] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   56.861961] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   56.862003] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.203185] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.203227] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.314141] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.314182] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   62.433335] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0

Rev D:

voodoo@labdev:~$ dmesg | grep tilcd
[    3.554544] [drm:tilcdc_drm_init] init
[    3.770701] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    3.770740] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    3.770756] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    3.770769] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    3.777654]  drm_atomic_helper_shutdown from tilcdc_fini+0x35/0x80
[    3.777677]  tilcdc_fini from tilcdc_init.constprop.0+0x175/0x494
[    3.777693]  tilcdc_init.constprop.0 from tilcdc_pdev_probe+0x3b/0x78
[    3.777707]  tilcdc_pdev_probe from platform_probe+0x41/0x6c
[    3.779223] tilcdc 4830e000.lcdc: [drm] *ERROR* Disabling all crtc's during unload failed with -12
[    6.396841] [drm:tilcdc_init.constprop.0] Configured for straight blue and red wires
[    6.396896] [drm:tilcdc_init.constprop.0] Maximum Bandwidth Value 78643200
[    6.396917] [drm:tilcdc_init.constprop.0] Maximum Horizontal Pixel Width Value 2048pixels
[    6.396934] [drm:tilcdc_init.constprop.0] Maximum Pixel Clock Value 126000KHz
[    6.494836] [drm] Initialized tilcdc 1.0.0 for 4830e000.lcdc on minor 0
[    6.518860] tilcdc 4830e000.lcdc: [drm] Cannot find any crtc or sizes
[    6.744779] [drm:tilcdc_crtc_mode_valid] Processing mode 1920x1080@60 with pixel clock 148500
[    6.744862] [drm:tilcdc_crtc_mode_valid] Pruning mode: pixel clock too high
[    6.744974] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@60 with pixel clock 81579
[    6.745085] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.745406] [drm:tilcdc_crtc_mode_valid] Processing mode 1600x900@60 with pixel clock 108000
[    6.745449] [drm:tilcdc_crtc_mode_valid] Pruning mode: exceeds defined bandwidth limit
[    6.745476] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    6.745588] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    6.745615] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    6.745725] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    6.745789] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    6.745817] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    6.745843] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    6.745906] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    6.774099] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.774161] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    6.774226] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.774261] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    6.789339] [drm:tilcdc_crtc_set_mode] 1280x1024, hbp=248, hfp=48, hsw=112, vbp=38, vfp=1, vsw=3
[    6.789826] [drm:tilcdc_crtc_set_clk] lcd_clk=216000000, mode clock=108000, div=2
[    6.790885] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[    6.807150] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.807190] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    6.828590] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    6.828631] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    7.189319] tilcdc 4830e000.lcdc: [drm] fb0: tilcdcdrmfb frame buffer device
[    7.379840] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    7.379981] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@60 with pixel clock 81579
[    7.380010] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    7.380075] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    7.380103] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    7.380167] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    7.380277] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    7.380387] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    7.380413] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    7.380439] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    7.380862] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    7.380906] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[    7.571772] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x1024@60 with pixel clock 108000
[    7.571916] [drm:tilcdc_crtc_mode_valid] Processing mode 1152x864@60 with pixel clock 81579
[    7.571947] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    7.572011] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74250
[    7.572039] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    7.572104] [drm:tilcdc_crtc_mode_valid] Processing mode 1280x720@60 with pixel clock 74176
[    7.572213] [drm:tilcdc_crtc_mode_valid] Processing mode 1024x768@60 with pixel clock 65000
[    7.572322] [drm:tilcdc_crtc_mode_valid] Processing mode 800x600@60 with pixel clock 40000
[    7.572349] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25200
[    7.572375] [drm:tilcdc_crtc_mode_valid] Processing mode 640x480@60 with pixel clock 25175
[    7.572799] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[    7.572842] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   12.769221] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0
[   55.111179] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   55.111220] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   55.111261] tilcdc 4830e000.lcdc: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[   57.247058] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.247100] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.314905] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.314946] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.701720] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.701761] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   57.738751] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
[   57.738792] tilcdc 4830e000.lcdc: [drm:drm_calc_timestamping_constants] crtc 35: clock 108000 kHz framedur 16661185 linedur 15629
[   62.945254] tilcdc 4830e000.lcdc: [drm:vblank_disable_fn] disabling vblank on crtc 0

So no to just wait for amazon.,..