The PMIC is not the problem here, it properly shuts down all DCDC and LDO supplies, and requires no configuration other than voltage adjustments when desired, and setting the OFF bit before using the RTC to request shutdown. (“SLEEP state” of the PMIC, aka “RTC-only sleep”, is not supported since vdds was moved from LDO3 to LDO1 in rev A6A.)
The issue is the interconnection of the 3v3a and 3v3b power domains, resulting in significant leakage current between them (e.g. via protection diodes) whenever one is powered while the other is not. The 3v3b → 3v3a leakage was of course exactly the reason for moving the enable-signal of the 3v3b regulator (U4) from 3v3aux (LDO2) to 3v3a. However, while this resolved the issue at boot, it did not resolve it at shutdown when running on dc power, and made it far worse when running on battery.
The problem is that when the 3v3a supply (LDO4) is disabled, the 3v3b regulator remains enabled until 3v3a drops below the threshold voltage of the enable-input of U4, which is far below 3.3V (specified to be somewhere between 0.4V (at 25 ͏°C) and 2V). As a result, current will start to flow from 3v3b to 3v3a, and apparently enough current to keep it logic-high in the opinion of the 3v3b-regulator (despite the ~375 ohm discharge resistor the PMIC applies when LDO4 is disabled!).
Thus, once turned on, the 3v3b regulator manages to keep itself enabled indefinitely as long as it is supplied from SYS_5V. When entering off-state, the PMIC automatically connects SYS to battery power rather than DC- or USB-supply. If there’s no battery, then the capacitors on SYS will drain pretty fast hence the 3v3b shutdown is not delayed much. If there’s a battery, then you’re pretty screwed.
It is very important to note that this issue is not merely one of battery lifetime; this leakage current may damage the processor.
To illustrate all this, let’s stare at some pretty pictures.
Here’s a capture of various power terminals during boot and shutdown while on DC power (click to zoom):
I’ve marked the PMIC sequencer “strobes” with vertical dashed lines, partially cut away when irrelevant or visually interfering with the signal plots. Unless noted otherwise, the interval between strobes is 1 ms.
As I mentioned, in off-state SYS is tied to BAT, and when DC-powered they hover around 1V for some reason (they’ll drop if you try to drain power from either, but once you stop they bounce back to 1V). All regulated supplies are off. Once the PMIC has detected a wakeup event, it connects SYS to the DC power supply, asserts the wakeup signal, and the sequencer powers up the “always-on” supplies:
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strobe 15: LDO1 (rtc, vdds)
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strobe 14: unused
The AM335x RTC asserts PW_EN and once debounced by the PMIC (~50 ms) the sequencer completes the power-on sequence:
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strobe 1: DCDC1 (ddr)
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strobe 2: LDO3 (1v8)
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[5 ms delay]
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strobe 3: LDO2 (3v3aux = power led)
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strobe 4: LDO4 (3v3a, enables 3v3b)
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strobe 5: DCDC2 (mpu), DCDC3 (core)
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strobe 6: unused
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strobe 7: unused
Meanwhile, since BATMON isn’t connected to BAT, the PMIC doesn’t really get what’s going on there. It seems to attempt to charge it for a while, then gives up, and later BAT somehow manages to drop below 0V and stay there (behaviour is quite different if BATMON is connected to BAT, in which case it’s pulsed a few times then drops to about 0.2V - 0.4V, apparently depending on system load).
When reentering off-state the PMIC shuts down the supplies in reverse order, with 1 ms between strobes 1 and 14. Strobe 7 is relevant this time because it marks when shutdown is initiated, and as a result SYS is disconnected from DC power and connects to BAT, which immediately shoots up to SYS level. Note however that 3v3b is not disabled at strobe 4 but stays slightly below SYS until long after the PMIC has completed shutdown. About 20 ms after it was supposed to, it finally begins to drop to zero while SYS, now unloaded and heavily supported by fat capacitors, begins its long and slow journey back towards the 1V.
For comparison, the same plot but now powered at 3.6V through BAT (using a variable power supply).
When BAT was powered up, SYS started tracking it once it reached 1V (hmm, sounds familiar), but the PMIC initially remains in off-state. The boot and shutdown are essentially the same, except SYS follows BAT continuously. As a result, once 3v3b is turned on, it remains on until power to BAT is cut.
Bottom line: if you want to run on battery power, this is a serious problem. You’ll need to keep the PMIC in active-state, though you can minimize power by commanding the ethernet phy and hdmi framer to power themselves down, and then enter a deepsleep mode. Alternatively, you’d need to patch the hardware, or have an external circuit detect this situation (3v3b on while 1v8_adc off) and disconnect the battery to resolve it.
