Is FIC0_AXI4_TARGET connection necessary for a custom DMA controller with LSRAM access?

BeagleV
,
1

Hi all,

I’m developing a custom DMA Controller and would appreciate some clarification regarding the FIC0_AXI4_TARGET port.

Project overview:

Transfer an image stored by the processor in LSRAM (0x60000000 - 0x61FFFFFF), perform hardware YUV-to-RGB conversion, and write the converted image to a different memory region (0x63000000 - 0x65FFFFFF).
My DMA_CONTROLLER_CUSTOM module includes:

  • APB_INTERFACE: Receives 4 APB writes via FIC3 (input image address, output image address, WIDTH, HEIGHT, and a START signal).
  • AXI4_READ_INTERFACE: Performs burst reads from the input address after receiving START.
  • FIFO_YUV: 256 positions of 64 bits each, to buffer the incoming data and prevent desynchronization, since for every 2 YUV reads, 3 RGB writes are needed.
  • YUV_TO_RGB_CONVERSION: Reads data from FIFO_YUV, converts 4 pixels at a time, and pushes results to FIFO_RGB.
  • FIFO_RGB: 256 positions of 64 bits each, to buffer outgoing converted data.
  • AXI4_WRITE_INTERFACE: Writes RGB data in bursts to the output address.
    An interrupt notifies the processor when the conversion and transfer are done.
    All memory transactions (read and write) are performed via FIC0; APB configuration is via FIC3.

Questions:

  1. In this context, is it necessary to connect the FIC0_AXI4_TARGET interface to anything, or is it safe to leave it unconnected if I’m only using custom AXI4 masters inside the FPGA fabric and not expecting external AXI masters to access my logic? I have attached the block diagram exported from Libero.
  2. How can I generate the bitstream to program the board directly from the Libero project using the change_gateware script, or at least by starting from the Libero project?
    block_diagram_with_custom_dma_controller.zip (183.2 KO)

Thanks in advance for any advice!