Um…has it already been decided what pins are what on the BONE-PWM0 - BONE-PWM2.kernel .DTBOs?
I am asking. I tried /overlays/BBAI64-P9_25-ehrpwm4_b.dtbo. For whatever reason, I had a LED shatter. Good power or lack of mechanical accessible moves. Either way, I am trying BONE-PWM0 - 2.kernel now.
Seth
P.S. I looked for the Compatible layer spec. recently and could not find the exact pin muxing for the BONE-PWM0 - 2.kernel pins…
I will keep testing. Oh. I also noticed, if anyone wants to jump in here:
I can echo 50000 > period and then echo 10000 > duty_cycle.
Then, I can echo 1 > enable.
The issue remains, when I try to use say in pwmchip0 the pwm1, I get an error when trying to use the pwm0 section of the same pwmchip0.
Here is the error in case anyone cares to comment:
@RobertCNelson , you are correct. I am sorry for only showing the first half of my actual commands.
cd /sys/class/pwmchip0
cd pwm1
echo 50000 > period
echo 10000 > duty_cycle
echo 1 > enable
echo 0 > enable
cd ../pwm0
echo 50000 > period
echo 10000 > duty_cycle
echo 1 > enable
That is how I came upon that error. I see what you typed recently about a and b channels.
Did I make a gaff or some huge mistake for the community who likes shared PWM channels?
Seth
P.S.
Sir, I cannot as my board set up only reveals the /dev/bone/uart/0 and not /dev/bone/pwm/* in that directory. I will keep trying to configure things correctly.
Is there an updated process on how to do PWM for the BeagleBone AI-64? I believe I followed the steps and get the devices to appear under /dev/bone, and I can change the period, duty cycle, and enable. However, I cannot seem to get the output to change in the pins themselves. My current test is an LED. I would expect it to get brighter for higher duty cycle but I don’t see any changes (it’s off for most PWM pins I’ve tried).
Is there a table or something somewhere in the documentation that tells which pins on the BBAI 64 expention headers are capable of PWM. Also I am looking for more info about the pins that that are connected to the Arm R5 and have PWM capability. I want to drive 6 servos
The R5 cores can access any of the pins. If you do a search with tag bbai64 and spreadsheet you should find a post by me with the header pins and the various pin mux alternatives
@RobertCNelson I checked and they were loaded. My issue ended up being that I didn’t realize there were 4 extra pins on P9 before normal indexing starts, and it seems both a and b need to be enabled for a given pwmchip. Thank you so much for your help!