What is known about PocketBeagle 2?

General Discussion
1

This document from TI from September 23 shows an image of the supposedly upcoming PocketBeagle 2.

Problem is I can’t find any other sources that mention it. Do we have any more information about this product or an idea of its expected release date? Will it work with existing capes?

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2

Hey,

It’s in the works, no final timeline yet except sometime Q4 but high level - AM6232 based, so Dual A53 + M4, same form factor as PB1 except no SIP now, it’s discrete with 512MB of RAM, still onboard EMMC, headers are compatible yes (final testing TBD but as much as physically possible after migrating to AM62 from 335) . Keep in mind because of higher PCB density the headers are now SMD on the bottom of the board.

3

Interesting, is there a reason for not going SiP? I ask because the OSD62x is releasing soon, also using a AM62. It would seem to be a natural progression for the PB to go from the OSD335 to the OSD62 so I would be curious to know what the reasoning is, if it is a matter of cost, sourcing it technical reasons.

4

Cost was the biggest factor, the guys worked really hard to hit a good price point on this one, this has also been in the works for quite a while so before OSD62x even had a defined ballmap.

There’s some other side benefits like potentially changing DDR size beyond 1GB either for prototyping or even some small run production. Nothing planned but there’s always the potential right.

5

SiP’s can be risky, as during the great semi shortage a few years back, discrete was way easier then SiP’s… (tps regulators…)

Regards,

6

Can you explain that a bit more? So the pins are not traditional header “pins” but like “smd pads”? Whats the approach for interfacing with them during development?

7

@Grippy98 It’s been a few months since your response and Pocketbeagle are impossible to find. Is there an update on the release of the Pocketbeagle 2? Expect price?
Thank you.

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8

Putting clues together on PB2 we can surmise that it will be based on AM6232 CPU, so it will have 2x A53 + 1 x M4 CPU.

Also @jkridner zephyr post also mentions an MSPM0…which is interesting. Wonder how that will be used?

9

The MSPM0 provides the ADC and board identifier EEPROM functions. Fortunately, this means that 8 of the MSPM0 pins will be on the header.

I can’t say much about the launch time. "real soon now"™.

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10

Any word about the price?

11

Do you know who will be manufacturing the PB2s?
Thank you.