How can I enable the 5 UARTs of the beaglebone AI-64?

DesaTecmmas · August 9, 2023, 6:33pm

How can I enable 5 UART ports, I tried adding the line “fdtoverlays /overlays/BONE-UART1.dtbo” in extlinux.conf but what it does is block the card and I have to load the firmware again.

foxsquirrel · August 9, 2023, 9:39pm

You would have to make your own device tree, I am not aware of 5 port tree. Believe the one you selected is only for 1 uart port. More than likely you will have to disable some other features to get that many, if it is even possible to have 5. @benedict.hewson any suggestions?

DesaTecmmas · August 9, 2023, 10:54pm

In the Beaglebone document it tells me that it can be done and to create the tree I need to “pinctrl register” the card, I don’t know where I can see that data.

foxsquirrel · August 10, 2023, 1:12am

Looks like if you add bone-uart4,5,6,7 to your start up file you should be working.

benedict.hewson · August 10, 2023, 6:21am

Ok as far as I can see, you can get 5 UARTS on top of the debug UART, Assuming there are no clashes.

These are the AI64 uarts and the header pins they are on. There are a few different options for some of these.

uart6 P9.14 (rx) P9.16 (tx)
uart2 P9.24 (tx) P9.26 (rx)
uart4 P9.37 (rx) P9.38 (tx)
uart8 P8.28 (rx) P8.29 (tx)
uart5 P8.38 (rx) P8.37 (tx)

Not sure why in the above table for the AI64 MAIN_UART0 and MAIN_UART2 are listed twice.

Some of the above uarts are on header pins connected to 2 MCU pins. These are usually labelled as ‘a’ and ‘b’ in the devicetree. You must make the alternate option for these pins as a GPIO input or you with get a clash and the function probably won’t work correctly.

benedict.hewson · August 10, 2023, 8:39am

Ok had trouble getting UART5 RX working, so ended up using an alternative pin.

So the below dts file enables 5 uarts and sets up the symlinks

/dev/bone/uart/2
/dev/bone/uart/4
/dev/bone/uart/5
/dev/bone/uart/6
/dev/bone/uart/8

I have tested this on my AI64, with only this overlay loaded and they are all working.

dts file

/dts-v1/;
/plugin/;

#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/board/k3-j721e-bone-pins.h>

&{/chosen} {
	overlays {
		BONE-UART_X5 = __TIMESTAMP__;
	};
};

&main_pmx0 {

	uartx5_2_pins_default:uartx5_2-pins-default {
		pinctrl-single,pins = <
		P9_24A(PIN_OUTPUT, 3) /* UART2 TX */
		P9_26A(PIN_INPUT, 3)  /* UART2 RX */
		P9_24B(PIN_INPUT, 7)
		P9_26B(PIN_INPUT, 7)
		>;
	};
	uartx5_4_pins_default:uartx5_4-pins-default {
		pinctrl-single,pins = <
		P9_37B(PIN_INPUT, 8)   /* UART4 RX */
		P9_38B(PIN_OUTPUT, 8)  /* UART4 TX */
		P9_37A(PIN_INPUT, 7)
		P9_38A(PIN_INPUT, 7)
		>;
	};
	uartx5_5_pins_default:uartx5_5-pins-default {
		pinctrl-single,pins = <
		P8_31B(PIN_INPUT, 14)  /* UART5 RX */
		P8_37A(PIN_OUTPUT, 3) /* UART5 TX */
		P8_31A(PIN_INPUT, 7)
		P8_37B(PIN_INPUT, 7)
		>;
	};
	uartx5_6_pins_default:uartx5_6-pins-default {
		pinctrl-single,pins = <
		P9_16(PIN_OUTPUT, 3)  /* UART6 TX */
		P9_14(PIN_INPUT, 3)   /* UART6 RX */
		>;
	};
	uartx5_8_pins_default:uartx5_8-pins-default {
		pinctrl-single,pins = <
		P8_29(PIN_OUTPUT, 14)  /* UART8 TX */
		P8_28(PIN_INPUT, 14)   /* UART8 RX */
		>;
	};

};

&main_uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uartx5_2_pins_default>;
	symlink = "bone/uart/2";
	status = "okay";
};

&main_uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uartx5_4_pins_default>;
	symlink = "bone/uart/4";
	status = "okay";
};

&main_uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&uartx5_5_pins_default>;
	symlink = "bone/uart/5";
	status = "okay";
};

&main_uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&uartx5_6_pins_default>;
	symlink = "bone/uart/6";
	status = "okay";
};

&main_uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&uartx5_8_pins_default>;
	symlink = "bone/uart/8";
	status = "okay";
};

Copy this file to your AI64. The extact path will depend on your kernel version.
On mine it is

/opt/source/dtb-5.10-ti/src/arm64/overlays/

Then from /opt/source/dtb-5.10-ti/ - ( sudo only needed if not root)

make && sudo make install

Add the overlay to your extlinux.conf file

fdtoverlays /overlays/uartx5.dtbo

Reboot and you should be up and running

DesaTecmmas · August 10, 2023, 3:57pm

I already did all the steps and it worked wonderfully, thank you very much for your help.

hank · October 13, 2023, 11:44am

Q. How to check the port is open?
→ I saw somewhere the command below is just checking the symlinks.

tree /dev/bone

.
.
.
+It’ll be very thankful if you point out the process that we need to change the files for enabling uart.

k3-j721e-beagleboneai64-bone-buses.dtsi

BONE_PIN(P8_37, uart,      P8_37A(PIN_OUTPUT, 3) P8_37B(PIN_INPUT, 7))	/* uart5_txd */
BONE_PIN(P8_38, uart,      P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 3))	/* uart5_rxd */
.
.
.
bone_uart_5: &main_uart5 {
	symlink = "bone/uart/5";
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <
		&P8_37_uart_pin /* uart5_txd */
		&P8_38_uart_pin /* uart5_rxd */
	>;
};

BONE-UART1.dts

&bone_uart_5 {
	status = "okay";
};

Of course I did ‘make && sudo make install’ + reboot
and added “/overlays/BONE-UART1.dtbo” on extlinux.conf

willtmakinen · October 14, 2024, 10:20am

For more information, I’m using the bbai64-debian-11.8-minimal-arm64-2023-10-07-4gb.img downloaded from BB’s website released a year ago and have run

sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-emmc.sh
sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-microsd.sh

to update uboot

willtmakinen · October 14, 2024, 10:20am

@benedict.hewson thank you for the info it has been very helpful.

I got things mostly working, however unfortunately only the RX pins of each port work. I.e., each of AI64’s uart ports can receive data from a serial but they can’t send anything back. I’ve tried several different serial programs (minicom, agetty) as well as just catting data directly to the bone/uart/ device to no avail. I tested the RX pin of my serial device (a USB to FTDI converter) and it works. I’ve also connected a logic analyzer to each UART’s TX pin and it is just stuck in a high state at 3.3V. I double-checked in the pin mux setting (number from 0-14) in the bone-buses.dtsi file and against the datsheet here https://www.ti.com/lit/ds/symlink/tda4vm.pdf and this spreadsheet Beagle bone AI64 pin mux - Google Sheets with no luck. I must be configuring all the device tree stuff correctly because otherwise the ports wouldn’t load under /dev/bone/uart (sudo beagle-version | grep UART shows all my uarts loading correctly), so there must be some mux or flag not being set correctly. Any thoughts on why this is? (edited)

benedict.hewson · October 14, 2024, 10:33am

Let me download that image and give it a go. I would guess as you mentioned in your other post it is a pinmux issue.
Just to speed things up which UARTs are you using and which header pins ?

benedict.hewson · October 14, 2024, 11:37am

Ok download the image and loaded the uartx5 overlay and I have all 5 UARTs working ok. Fully tested.

Out of curiosity when using minicom did you make sure that hardware flow control is off. I think by default it is enabled. That will stop transmits from working.

mithunnj · January 28, 2025, 10:49pm

Hi @benedict.hewson thank you for the clarification from above. Below is a summary of what worked for us to enable 4x UARTS:

Problem We Were Trying to Solve
We needed to enable and configure all 5 UARTs available on the BeagleBone AI-64. Additionally, we aim to expand this to include configurations for 4xCAN and 2xGPIO to suit our application’s needs. This thread serves as a reference for enabling UARTs, with follow-up questions related to the CAN and GPIO configurations.

Background on Our Implementation

The base image that we chose to go with: bbai64-debian-11.8-minimal-arm64-2023-10-07-4gb.img
- This image enabled us to expose the necessary UART peripherals. We didn’t have success with newer images.
  Note: Post deployment we needed to run these steps on the BeagleBone Ai64:

sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-emmc.sh
sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-microsd.sh

Our Device Tree Changes

k3-j721e-beagleboneai64-bone-buses.dtsi
This includes our UART nodes, Pinmux configurations:

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/board/k3-j721e-bone-pins.h>
#include <dt-bindings/pinctrl/k3.h>

/* MYTRA NOTE: DO NOT MODIFY THE BUS PINMUX SETTINGS OUTLINED BELOW */

ocp: &main_pmx0 {
/* macro: BONE_PIN( <pin>, <mode_name>, <register_value_macro(s)>) */
#define BONE_PIN(XX,ZZ,QQ) \
	XX##_##ZZ##_pin: pinmux_##XX##_##ZZ##_pin { pinctrl-single,pins = < QQ >; };

	/* I2C: https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#i2c */
	/* bone_i2c_1 main_i2c6 P9.17 P9.18 */
	/* bone_i2c_2 main_i2c2 P9.19 P9.20 */
	/* bone_i2c_3 main_i2c4 P9.24 P9.26 */

	/* CAN: https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#can */
	/* bone_can_0 main_mcan0 P9.20 P9.19 */
	/* bone_can_1 main_mcan4 P9.26 P9.24 */
	/* bone_can_2 main_mcan5 P8.08 P8.07 */
	/* bone_can_3 main_mcan6 P8.10 P8.09 */
	/* bone_can_4 main_mcan7 P8.05 P8.06 */

	/* SPI : https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#spi */
	/* bone_spi_0 main_spi6 P9.18 P9.21 P9.22 P9.16 P9.23 */
	/* bone_spi_1 main_spi7 P9.30 P9.29 P9.31 P9.29 P9.42 */

	/* UART : https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#uart */
	/* bone_uart_1 main_uart2 P9.24 P9.22 */
	/* bone_uart_4 main_uart0 P9.13 P9.11 */
	/* bone_uart_5 main_uart5 P8.37 P8.38 P8.32 P8.31 */
	/* bone_uart_6 main_uart8 P8.29 P8.28 */
	/* bone_uart_7 main_uart2 P8.34 P8.22 */

	/* PWM: https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#pwm */
	/* bone_pwm_0 ehrpwm1 P9.22 P9.21 */
	/* bone_pwm_1 ehrpwm2 P9.14 P9.16 */
	/* bone_pwm_2 ehrpwm0 P8.19 P8.13 */

	/* Full P8/P9 header mode definitions */
	/* P8_01 - GND */
	/* P8_02 - GND */

	/* P8_03 (AH21) PRG1_PRU0_GPO19 (gpio0_20) AH21_MCAN6_TX */
	BONE_PIN(P8_03, default,   P8_03(PIN_INPUT, 7))
	BONE_PIN(P8_03, pruout,    P8_03(PIN_OUTPUT, 0))	/* prg1_pru0_gpo19 */
	BONE_PIN(P8_03, pruin,     P8_03(PIN_INPUT, 1))		/* prg1_pru0_gpi19 */
	BONE_PIN(P8_03, can,       P8_03(PIN_INPUT, 6))		/* mcan6_tx */
	BONE_PIN(P8_03, gpio,      P8_03(PIN_INPUT, 7))
	BONE_PIN(P8_03, gpio_pu,   P8_03(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_03, gpio_pd,   P8_03(PIN_INPUT_PULLDOWN, 7))

	/* P8_04 (AC29) PRG0_PRU0_GPO5 (gpio0_48) AC29_SYS_BOOTMODE2 */
	BONE_PIN(P8_04, default,   P8_04(PIN_INPUT, 7))
	BONE_PIN(P8_04, pruout,    P8_04(PIN_OUTPUT, 0))	/* prg0_pru0_gpo5 */
	BONE_PIN(P8_04, pruin,     P8_04(PIN_INPUT, 1))		/* prg0_pru0_gpi5 */
	BONE_PIN(P8_04, gpio,      P8_04(PIN_INPUT, 7))
	BONE_PIN(P8_04, gpio_pu,   P8_04(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_04, gpio_pd,   P8_04(PIN_INPUT_PULLDOWN, 7))

	/* P8_05 (AH25) PRG1_PRU1_GPO12 (gpio0_33) AH25_MCAN7_TX */
	BONE_PIN(P8_05, default,   P8_05(PIN_INPUT, 7))
	BONE_PIN(P8_05, pruout,    P8_05(PIN_OUTPUT, 0))	/* prg1_pru1_gpo12 */
	BONE_PIN(P8_05, pruin,     P8_05(PIN_INPUT, 1))		/* prg1_pru1_gpi12 */
	BONE_PIN(P8_05, can,       P8_05(PIN_INPUT, 6))		/* mcan7_tx */
	BONE_PIN(P8_05, gpio,      P8_05(PIN_INPUT, 7))
	BONE_PIN(P8_05, gpio_pu,   P8_05(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_05, gpio_pd,   P8_05(PIN_INPUT_PULLDOWN, 7))

	/* P8_06 (AG25) PRG1_PRU1_GPO13 (gpio0_34) AG25_MCAN7_RX */
	BONE_PIN(P8_06, default,   P8_06(PIN_INPUT, 7))
	BONE_PIN(P8_06, pruout,    P8_06(PIN_OUTPUT, 0))	/* prg1_pru1_gpo13 */
	BONE_PIN(P8_06, pruin,     P8_06(PIN_INPUT, 1))		/* prg1_pru1_gpi13 */
	BONE_PIN(P8_06, can,       P8_06(PIN_INPUT, 6))		/* mcan7_rx */
	BONE_PIN(P8_06, gpio,      P8_06(PIN_INPUT, 7))
	BONE_PIN(P8_06, gpio_pu,   P8_06(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_06, gpio_pd,   P8_06(PIN_INPUT_PULLDOWN, 7))

	/* P8_07 (AD24) PRG1_PRU0_GPO14 (gpio0_15) AD24_MCAN5_RX */
	BONE_PIN(P8_07, default,   P8_07(PIN_INPUT, 7))
	BONE_PIN(P8_07, pruout,    P8_07(PIN_OUTPUT, 0))	/* prg1_pru0_gpo14 */
	BONE_PIN(P8_07, pruin,     P8_07(PIN_INPUT, 1))		/* prg1_pru0_gpi14 */
	BONE_PIN(P8_07, can,       P8_07(PIN_INPUT, 6))		/* mcan5_rx */
	BONE_PIN(P8_07, gpio,      P8_07(PIN_INPUT, 7))
	BONE_PIN(P8_07, gpio_pu,   P8_07(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_07, gpio_pd,   P8_07(PIN_INPUT_PULLDOWN, 7))

	/* P8_08 (AG24) PRG1_PRU0_GPO13 (gpio0_14) AG24_MCAN5_TX */
	BONE_PIN(P8_08, default,   P8_08(PIN_INPUT, 7))
	BONE_PIN(P8_08, pruout,    P8_08(PIN_OUTPUT, 0))	/* prg1_pru0_gpo13 */
	BONE_PIN(P8_08, pruin,     P8_08(PIN_INPUT, 1))		/* prg1_pru0_gpi13 */
	BONE_PIN(P8_08, can,       P8_08(PIN_OUTPUT, 6))	/* mcan5_tx */
	BONE_PIN(P8_08, gpio,      P8_08(PIN_INPUT, 7))
	BONE_PIN(P8_08, gpio_pu,   P8_08(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_08, gpio_pd,   P8_08(PIN_INPUT_PULLDOWN, 7))

	/* P8_09 (AE24) PRG1_PRU0_GPO16 (gpio0_17) AE24_MCAN6_RX */
	BONE_PIN(P8_09, default,   P8_09(PIN_INPUT, 7))
	BONE_PIN(P8_09, pruout,    P8_09(PIN_OUTPUT, 0))	/* prg1_pru0_gpo16 */
	BONE_PIN(P8_09, pruin,     P8_09(PIN_INPUT, 1))		/* prg1_pru0_gpi16 */
	BONE_PIN(P8_09, can,       P8_09(PIN_INPUT, 6))		/* mcan6_rx */
	BONE_PIN(P8_09, gpio,      P8_09(PIN_INPUT, 7))
	BONE_PIN(P8_09, gpio_pu,   P8_09(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_09, gpio_pd,   P8_09(PIN_INPUT_PULLDOWN, 7))

	/* P8_10 (AC24) PRG1_PRU0_GPO15 (gpio0_16) AC24_MCAN6_TX */
	BONE_PIN(P8_10, default,   P8_10(PIN_INPUT, 7))
	BONE_PIN(P8_10, pruout,    P8_10(PIN_OUTPUT, 0))	/* prg1_pru0_gpo15 */
	BONE_PIN(P8_10, pruin,     P8_10(PIN_INPUT, 1))		/* prg1_pru0_gpi15 */
	BONE_PIN(P8_10, can,       P8_10(PIN_INPUT, 7))		/* mcan6_tx */
	BONE_PIN(P8_10, gpio,      P8_10(PIN_INPUT, 7))
	BONE_PIN(P8_10, gpio_pu,   P8_10(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_10, gpio_pd,   P8_10(PIN_INPUT_PULLDOWN, 7))

	/* P8_11 (AB24) PRG0_PRU0_GPO17 (gpio0_60) AB24_SYS_BOOTMODE7 */
	BONE_PIN(P8_11, default,   P8_11(PIN_INPUT, 7))
	BONE_PIN(P8_11, pruout,    P8_11(PIN_OUTPUT, 0))	/* prg0_pru0_gpo17 */
	BONE_PIN(P8_11, pruin,     P8_11(PIN_INPUT, 1))		/* prg0_pru0_gpi17 */
	BONE_PIN(P8_11, gpio,      P8_11(PIN_INPUT, 7))
	BONE_PIN(P8_11, gpio_pu,   P8_11(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_11, gpio_pd,   P8_11(PIN_INPUT_PULLDOWN, 7))

	/* P8_12 (AH28) PRG0_PRU0_GPO16 (gpio0_59) AH28_PRG0_PWM0_A2 */
	BONE_PIN(P8_12, default,   P8_12(PIN_INPUT, 7))
	BONE_PIN(P8_12, pruout,    P8_12(PIN_OUTPUT, 0))	/* prg0_pru0_gpo16 */
	BONE_PIN(P8_12, pruin,     P8_12(PIN_INPUT, 1))		/* prg0_pru0_gpi16 */
	BONE_PIN(P8_12, gpio,      P8_12(PIN_INPUT, 7))
	BONE_PIN(P8_12, gpio_pu,   P8_12(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_12, gpio_pd,   P8_12(PIN_INPUT_PULLDOWN, 7))

	/* P8_13 (V27) RGMII5_TD1 (gpio0_89) V27_EHRPWM0_B */
	BONE_PIN(P8_13, default,   P8_13(PIN_INPUT, 7))
	BONE_PIN(P8_13, gpio,      P8_13(PIN_INPUT, 7))
	BONE_PIN(P8_13, gpio_pu,   P8_13(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_13, gpio_pd,   P8_13(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_13, pwm,       P8_13(PIN_OUTPUT, 6))	/* ehrpwm0_b */

	/* P8_14 (AF27) PRG0_PRU1_GPO12 (gpio0_75) AF27_PRG0_PWM1_A0 */
	BONE_PIN(P8_14, default,   P8_14(PIN_INPUT, 7))
	BONE_PIN(P8_14, pruout,    P8_14(PIN_OUTPUT, 0))	/* prg0_pru1_gpo12 */
	BONE_PIN(P8_14, pruin,     P8_14(PIN_INPUT, 1))		/* prg0_pru1_gpi12 */
	BONE_PIN(P8_14, gpio,      P8_14(PIN_INPUT, 7))
	BONE_PIN(P8_14, gpio_pu,   P8_14(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_14, gpio_pd,   P8_14(PIN_INPUT_PULLDOWN, 7))

	/* P8_15 (AB29) PRG0_PRU0_GPO18 (gpio0_61) AB29_PRG0_ECAP0_IN_APWM_OUT */
	BONE_PIN(P8_15, default,   P8_15(PIN_INPUT, 7))
	BONE_PIN(P8_15, pruout,    P8_15(PIN_OUTPUT, 0))	/* prg0_pru0_gpo18 */
	BONE_PIN(P8_15, pruin,     P8_15(PIN_INPUT, 1))		/* prg0_pru0_gpi18 */
	BONE_PIN(P8_15, gpio,      P8_15(PIN_INPUT, 7))
	BONE_PIN(P8_15, gpio_pu,   P8_15(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_15, gpio_pd,   P8_15(PIN_INPUT_PULLDOWN, 7))

	/* P8_16 (AB28) PRG0_PRU0_GPO19 (gpio0_62) AB28_PRG0_PWM0_TZ_OUT */
	BONE_PIN(P8_16, default,   P8_16(PIN_INPUT, 7))
	BONE_PIN(P8_16, pruout,    P8_16(PIN_OUTPUT, 0))	/* prg0_pru0_gpo19 */
	BONE_PIN(P8_16, pruin,     P8_16(PIN_INPUT, 1))		/* prg0_pru0_gpi19 */
	BONE_PIN(P8_16, gpio,      P8_16(PIN_INPUT, 7))
	BONE_PIN(P8_16, gpio_pu,   P8_16(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_16, gpio_pd,   P8_16(PIN_INPUT_PULLDOWN, 7))

	/* P8_17 (AF22) PRG1_PRU0_GPO2 (gpio0_3) AF22_PRG1_PWM2_A0 */
	BONE_PIN(P8_17, default,   P8_17(PIN_INPUT, 7))
	BONE_PIN(P8_17, pruout,    P8_17(PIN_OUTPUT, 0))	/* prg1_pru0_gpo2 */
	BONE_PIN(P8_17, pruin,     P8_17(PIN_INPUT, 1))		/* prg1_pru0_gpi2 */
	BONE_PIN(P8_17, gpio,      P8_17(PIN_INPUT, 7))
	BONE_PIN(P8_17, gpio_pu,   P8_17(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_17, gpio_pd,   P8_17(PIN_INPUT_PULLDOWN, 7))

	/* P8_18 (AJ23) PRG1_PRU0_GPO3 (gpio0_4) AJ23_PRG1_PWM3_A2 */
	BONE_PIN(P8_18, default,   P8_18(PIN_INPUT, 7))
	BONE_PIN(P8_18, pruout,    P8_18(PIN_OUTPUT, 0))	/* prg1_pru0_gpo3 */
	BONE_PIN(P8_18, pruin,     P8_18(PIN_INPUT, 1))		/* prg1_pru0_gpi3 */
	BONE_PIN(P8_18, gpio,      P8_18(PIN_INPUT, 7))
	BONE_PIN(P8_18, gpio_pu,   P8_18(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_18, gpio_pd,   P8_18(PIN_INPUT_PULLDOWN, 7))

	/* P8_19 (V29) RGMII5_TD2 (gpio0_88) V29_EHRPWM0_A */
	BONE_PIN(P8_19, default,   P8_19(PIN_INPUT, 7))
	BONE_PIN(P8_19, gpio,      P8_19(PIN_INPUT, 7))
	BONE_PIN(P8_19, gpio_pu,   P8_19(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_19, gpio_pd,   P8_19(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_19, pwm,       P8_19(PIN_OUTPUT, 6))	/* ehrpwm0_a */

	/* P8_20 (AF26) PRG0_PRU1_GPO13 (gpio0_76) AF26_PRG0_PWM1_B0 */
	BONE_PIN(P8_20, default,   P8_20(PIN_INPUT, 7))
	BONE_PIN(P8_20, pruout,    P8_20(PIN_OUTPUT, 0))	/* prg0_pru1_gpo13 */
	BONE_PIN(P8_20, pruin,     P8_20(PIN_INPUT, 1))		/* prg0_pru1_gpi13 */
	BONE_PIN(P8_20, gpio,      P8_20(PIN_INPUT, 7))
	BONE_PIN(P8_20, gpio_pu,   P8_20(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_20, gpio_pd,   P8_20(PIN_INPUT_PULLDOWN, 7))

	/* P8_21 (AF21) PRG1_PRU1_GPO9 (gpio0_30) AF21_MCAN8_TX */
	BONE_PIN(P8_21, default,   P8_21(PIN_INPUT, 7))
	BONE_PIN(P8_21, pruout,    P8_21(PIN_OUTPUT, 0))	/* prg1_pru1_gpo9 */
	BONE_PIN(P8_21, pruin,     P8_21(PIN_INPUT, 1))		/* prg1_pru1_gpi9 */
	BONE_PIN(P8_21, gpio,      P8_21(PIN_INPUT, 7))
	BONE_PIN(P8_21, gpio_pu,   P8_21(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_21, gpio_pd,   P8_21(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_21, spi,       P8_21(PIN_OUTPUT, 4))	/* spi6_cs3 */

	/* P8_22 (AH23) PRG1_PRU0_GPO4 (gpio0_5) AH23_UART2_RXD */
	BONE_PIN(P8_22, default,   P8_22(PIN_INPUT, 7))
	BONE_PIN(P8_22, pruout,    P8_22(PIN_OUTPUT, 0))	/* prg1_pru0_gpo4 */
	BONE_PIN(P8_22, pruin,     P8_22(PIN_INPUT, 1))		/* prg1_pru0_gpi4 */
	BONE_PIN(P8_22, gpio,      P8_22(PIN_INPUT, 7))
	BONE_PIN(P8_22, gpio_pu,   P8_22(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_22, gpio_pd,   P8_22(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_22, uart,      P8_22(PIN_INPUT, 14))	/* uart2_rxd */

	/* P8_23 (AB23) PRG1_PRU1_GPO10 (gpio0_31) AB23_MCAN8_RX */
	BONE_PIN(P8_23, default,   P8_23(PIN_INPUT, 7))
	BONE_PIN(P8_23, pruout,    P8_23(PIN_OUTPUT, 0))	/* prg1_pru1_gpo10 */
	BONE_PIN(P8_23, pruin,     P8_23(PIN_INPUT, 1))		/* prg1_pru1_gpi10 */
	BONE_PIN(P8_23, pruuart,   P8_23(PIN_OUTPUT, 2))
	BONE_PIN(P8_23, gpio,      P8_23(PIN_INPUT, 7))
	BONE_PIN(P8_23, gpio_pu,   P8_23(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_23, gpio_pd,   P8_23(PIN_INPUT_PULLDOWN, 7))

	/* P8_24 (AD20) PRG1_PRU0_GPO5 (gpio0_6) AD20_SYS_BOOTMODE0 */
	BONE_PIN(P8_24, default,   P8_24(PIN_INPUT, 7))
	BONE_PIN(P8_24, pruout,    P8_24(PIN_OUTPUT, 0))	/* prg1_pru0_gpo5 */
	BONE_PIN(P8_24, pruin,     P8_24(PIN_INPUT, 1))		/* prg1_pru0_gpi5 */
	BONE_PIN(P8_24, gpio,      P8_24(PIN_INPUT, 7))
	BONE_PIN(P8_24, gpio_pu,   P8_24(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_24, gpio_pd,   P8_24(PIN_INPUT_PULLDOWN, 7))

	/* P8_25 (AH26) PRG1_PRU1_GPO14 (gpio0_35) AH26_PRG1_PRU1_GPO14 */
	BONE_PIN(P8_25, default,   P8_25(PIN_INPUT, 7))
	BONE_PIN(P8_25, pruout,    P8_25(PIN_OUTPUT, 0))	/* prg1_pru1_gpo14 */
	BONE_PIN(P8_25, pruin,     P8_25(PIN_INPUT, 1))		/* prg1_pru1_gpi14 */
	BONE_PIN(P8_25, gpio,      P8_25(PIN_INPUT, 7))
	BONE_PIN(P8_25, gpio_pu,   P8_25(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_25, gpio_pd,   P8_25(PIN_INPUT_PULLDOWN, 7))

	/* P8_26 (AC27) PRG0_PRU0_GPO8 (gpio0_51) AC27_PRG0_PWM2_A1 */
	BONE_PIN(P8_26, default,   P8_26(PIN_INPUT, 7))
	BONE_PIN(P8_26, pruout,    P8_26(PIN_OUTPUT, 0))	/* prg0_pru0_gpo8 */
	BONE_PIN(P8_26, pruin,     P8_26(PIN_INPUT, 1))		/* prg0_pru0_gpi8 */
	BONE_PIN(P8_26, gpio,      P8_26(PIN_INPUT, 7))
	BONE_PIN(P8_26, gpio_pu,   P8_26(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_26, gpio_pd,   P8_26(PIN_INPUT_PULLDOWN, 7))

	/* P8_27 (AA28) PRG0_PRU1_GPO8 (gpio0_71) AA28_PRG0_PRU1_GPO8 */
	BONE_PIN(P8_27, default,   P8_27(PIN_INPUT, 7))
	BONE_PIN(P8_27, pruout,    P8_27(PIN_OUTPUT, 0))	/* prg0_pru1_gpo8 */
	BONE_PIN(P8_27, pruin,     P8_27(PIN_INPUT, 1))		/* prg0_pru1_gpi8 */
	BONE_PIN(P8_27, gpio,      P8_27(PIN_INPUT, 7))
	BONE_PIN(P8_27, gpio_pu,   P8_27(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_27, gpio_pd,   P8_27(PIN_INPUT_PULLDOWN, 7))

	/* P8_28 (Y24) PRG0_PRU1_GPO9 (gpio0_72) Y24_PRG0_UART0_RXD */
	BONE_PIN(P8_28, default,   P8_28(PIN_INPUT, 7))
	BONE_PIN(P8_28, pruout,    P8_28(PIN_OUTPUT, 0))	/* prg0_pru1_gpo9 */
	BONE_PIN(P8_28, pruin,     P8_28(PIN_INPUT, 1))		/* prg0_pru1_gpi9 */
	BONE_PIN(P8_28, gpio,      P8_28(PIN_INPUT, 7))
	BONE_PIN(P8_28, gpio_pu,   P8_28(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_28, gpio_pd,   P8_28(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_28, uart,      P8_28(PIN_INPUT, 14))	/* uart8_rx */

	/* P8_29 (AA25) PRG0_PRU1_GPO10 (gpio0_73) AA25_PRG0_UART0_TXD */
	BONE_PIN(P8_29, default,   P8_29(PIN_INPUT, 7))
	BONE_PIN(P8_29, pruout,    P8_29(PIN_OUTPUT, 0))	/* prg0_pru1_gpo10 */
	BONE_PIN(P8_29, pruin,     P8_29(PIN_INPUT, 1))		/* prg0_pru1_gpi10 */
	BONE_PIN(P8_29, gpio,      P8_29(PIN_INPUT, 7))
	BONE_PIN(P8_29, gpio_pu,   P8_29(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_29, gpio_pd,   P8_29(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_29, uart,      P8_29(PIN_OUTPUT, 14))	/* uart8_tx */

	/* P8_30 (AG26) PRG0_PRU1_GPO11 (gpio0_74) AG26_PRG0_PRU1_GPO11 */
	BONE_PIN(P8_30, default,   P8_30(PIN_INPUT, 7))
	BONE_PIN(P8_30, pruout,    P8_30(PIN_OUTPUT, 0))	/* prg0_pru1_gpo11 */
	BONE_PIN(P8_30, pruin,     P8_30(PIN_INPUT, 1))		/* prg0_pru1_gpi11 */
	BONE_PIN(P8_30, gpio,      P8_30(PIN_INPUT, 7))
	BONE_PIN(P8_30, gpio_pu,   P8_30(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_30, gpio_pd,   P8_30(PIN_INPUT_PULLDOWN, 7))

	/* P8_31 (AJ25/AE29) PRG1_PRU1_GPO11/PRG0_PRU1_GPO0 (gpio0_32/gpio0_63) AJ25_AE29 */
	BONE_PIN(P8_31, default,   P8_31A(PIN_INPUT, 7) P8_31B(PIN_INPUT, 7))
	BONE_PIN(P8_31, pruout,    P8_31A(PIN_OUTPUT, 0) P8_31B(PIN_INPUT, 7))
	BONE_PIN(P8_31, pruin,     P8_31A(PIN_INPUT, 1) P8_31B(PIN_INPUT, 7))
	BONE_PIN(P8_31, gpio,      P8_31A(PIN_INPUT, 7) P8_31B(PIN_INPUT, 7))	/* gpio0_32 */
	BONE_PIN(P8_31, gpio_pu,   P8_31A(PIN_INPUT_PULLUP, 7) P8_31B(PIN_INPUT, 7))
	BONE_PIN(P8_31, gpio_pd,   P8_31A(PIN_INPUT_PULLDOWN, 7) P8_31B(PIN_INPUT, 7))
	BONE_PIN(P8_31, qep,       P8_31A(PIN_INPUT, 9) P8_31B(PIN_INPUT, 7))	/* eqep1_i */
	BONE_PIN(P8_31, uart,      P8_31A(PIN_INPUT, 7) P8_31B(PIN_INPUT, 14))	/* uart5_rxd */

	/* P8_32 (AG21/AD28) PRG1_PRU1_GPO5/PRG0_PRU1_GPO1 (gpio0_26/gpio0_64) AG21_AD28 */
	BONE_PIN(P8_32, default,   P8_32A(PIN_INPUT, 7) P8_32B(PIN_INPUT, 7))
	BONE_PIN(P8_32, pruout,    P8_32A(PIN_OUTPUT, 0) P8_32B(PIN_INPUT, 7))
	BONE_PIN(P8_32, pruin,     P8_32A(PIN_INPUT, 1) P8_32B(PIN_INPUT, 7))
	BONE_PIN(P8_32, gpio,      P8_32A(PIN_INPUT, 7) P8_32B(PIN_INPUT, 7))	/* gpio0_26 */
	BONE_PIN(P8_32, gpio_pu,   P8_32A(PIN_INPUT_PULLUP, 7) P8_32B(PIN_INPUT, 7))
	BONE_PIN(P8_32, gpio_pd,   P8_32A(PIN_INPUT_PULLDOWN, 7) P8_32B(PIN_INPUT, 7))
	BONE_PIN(P8_32, qep,       P8_32A(PIN_INPUT, 9) P8_32B(PIN_INPUT, 7))	/* eqep1_s */
	BONE_PIN(P8_32, uart,      P8_32A(PIN_INPUT, 7) P8_32B(PIN_OUTPUT, 14))	/* uart5_txd */

	/* P8_33 (AH24/AA2) PRG1_PRU1_GPO4/SPI0_CS0 (gpio0_25/gpio0_111) AH24_AA2 */
	BONE_PIN(P8_33, default,   P8_33A(PIN_INPUT, 7) P8_33B(PIN_INPUT, 7))
	BONE_PIN(P8_33, pruout,    P8_33A(PIN_OUTPUT, 0) P8_33B(PIN_INPUT, 7))	/* prg1_pru1_gpo4 */
	BONE_PIN(P8_33, pruin,     P8_33A(PIN_INPUT, 1) P8_33B(PIN_INPUT, 7))	/* prg1_pru1_gpi4 */
	BONE_PIN(P8_33, gpio,      P8_33A(PIN_INPUT, 7) P8_33B(PIN_INPUT, 7))	/* gpio0_25 */
	BONE_PIN(P8_33, gpio_pu,   P8_33A(PIN_INPUT_PULLUP, 7) P8_33B(PIN_INPUT, 7))
	BONE_PIN(P8_33, gpio_pd,   P8_33A(PIN_INPUT_PULLDOWN, 7) P8_33B(PIN_INPUT, 7))
	BONE_PIN(P8_33, qep,       P8_33A(PIN_INPUT, 9) P8_33B(PIN_INPUT, 7))	/* eqep1_b */

	/* P8_34 (AD22) PRG1_PRU0_GPO6 (gpio0_7) AD22_UART2_TXD */
	BONE_PIN(P8_34, default,   P8_34(PIN_INPUT, 7))
	BONE_PIN(P8_34, pruout,    P8_34(PIN_OUTPUT, 0))	/* prg1_pru0_gpo6 */
	BONE_PIN(P8_34, pruin,     P8_34(PIN_INPUT, 1))		/* prg1_pru0_gpi6 */
	BONE_PIN(P8_34, gpio,      P8_34(PIN_INPUT, 7))
	BONE_PIN(P8_34, gpio_pu,   P8_34(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_34, gpio_pd,   P8_34(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_34, uart,      P8_34(PIN_OUTPUT, 14))	/* uart2_txd */

	/* P8_35 (AD23/Y3) PRG1_PRU1_GPO3/SPI1_CS0 (gpio0_24/gpio0_116) AD23_Y3 */
	BONE_PIN(P8_35, default,   P8_35A(PIN_INPUT, 7) P8_35B(PIN_INPUT, 7))
	BONE_PIN(P8_35, pruout,    P8_35A(PIN_OUTPUT, 0) P8_35B(PIN_INPUT, 7))	/* prg1_pru1_gpo3 */
	BONE_PIN(P8_35, pruin,     P8_35A(PIN_INPUT, 1) P8_35B(PIN_INPUT, 7))	/* prg1_pru1_gpi3 */
	BONE_PIN(P8_35, gpio,      P8_35A(PIN_INPUT, 7) P8_35B(PIN_INPUT, 7))	/* gpio0_24 */
	BONE_PIN(P8_35, gpio_pu,   P8_35A(PIN_INPUT_PULLUP, 7) P8_35B(PIN_INPUT, 7))
	BONE_PIN(P8_35, gpio_pd,   P8_35A(PIN_INPUT_PULLDOWN, 7) P8_35B(PIN_INPUT, 7))
	BONE_PIN(P8_35, qep,       P8_35A(PIN_INPUT, 9) P8_35B(PIN_INPUT, 7))	/* eqep1_a */
	BONE_PIN(P8_35, uart,      P8_35A(PIN_INPUT, 7) P8_35B(PIN_INPUT, 3))	/* uart5_rxd */

	/* P8_36 (AE20) PRG1_PRU0_GPO7 (gpio0_8) AE20_MCAN4_TX */
	BONE_PIN(P8_36, default,   P8_36(PIN_INPUT, 7))
	BONE_PIN(P8_36, pruout,    P8_36(PIN_OUTPUT, 0))	/* prg1_pru0_gpo7 */
	BONE_PIN(P8_36, pruin,     P8_36(PIN_INPUT, 1))		/* prg1_pru0_gpi7 */
	BONE_PIN(P8_36, can,       P8_36(PIN_OUTPUT, 6))	/* mcan4_tx */
	BONE_PIN(P8_36, gpio,      P8_36(PIN_INPUT, 7))
	BONE_PIN(P8_36, gpio_pu,   P8_36(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_36, gpio_pd,   P8_36(PIN_INPUT_PULLDOWN, 7))

	/* P8_37 (Y27/AD21) RGMII6_RD2/PRG1_PRU0_GPO10 (gpio0_106/gpio0_11) Y27_AD21 */
	BONE_PIN(P8_37, default,   P8_37A(PIN_INPUT, 7) P8_37B(PIN_INPUT, 7))
	BONE_PIN(P8_37, pruout,    P8_37A(PIN_INPUT, 7) P8_37B(PIN_OUTPUT, 0))	/* prg1_pru0_gpo10 */
	BONE_PIN(P8_37, pruin,     P8_37A(PIN_INPUT, 7) P8_37B(PIN_INPUT, 1))	/* prg1_pru0_gpi10 */
	BONE_PIN(P8_37, gpio,      P8_37A(PIN_INPUT, 7) P8_37B(PIN_INPUT, 7))	/* gpio0_106 */
	BONE_PIN(P8_37, gpio_pu,   P8_37A(PIN_INPUT_PULLUP, 7) P8_37B(PIN_INPUT, 7))
	BONE_PIN(P8_37, gpio_pd,   P8_37A(PIN_INPUT_PULLDOWN, 7) P8_37B(PIN_INPUT, 7))
	BONE_PIN(P8_37, pwm,       P8_37A(PIN_OUTPUT, 6) P8_37B(PIN_INPUT, 7))	/* ehrpwm5_a */
	BONE_PIN(P8_37, spi,       P8_37A(PIN_INPUT, 7) P8_37B(PIN_OUTPUT, 4))	/* spi6_cs2 */
	BONE_PIN(P8_37, uart,      P8_37A(PIN_OUTPUT, 3) P8_37B(PIN_INPUT, 7))	/* uart5_txd */

	/* P8_38 (AJ20/Y29) PRG1_PRU0_GPO8/RGMII6_RD3 (gpio0_9/gpio0_105) Y29_AJ20 */
	BONE_PIN(P8_38, default,   P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 7))
	BONE_PIN(P8_38, pruout,    P8_38A(PIN_OUTPUT, 0) P8_38B(PIN_INPUT, 7))	/* prg1_pru0_gpo8 */
	BONE_PIN(P8_38, pruin,     P8_38A(PIN_INPUT, 1) P8_38B(PIN_INPUT, 7))	/* prg1_pru0_gpi8 */
	BONE_PIN(P8_38, can,       P8_38A(PIN_INPUT, 6) P8_38B(PIN_INPUT, 7))	/* mcan4_rx */
	BONE_PIN(P8_38, gpio,      P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 7))	/* gpio0_9 */
	BONE_PIN(P8_38, gpio_pu,   P8_38A(PIN_INPUT_PULLUP, 7) P8_38B(PIN_INPUT, 7))
	BONE_PIN(P8_38, gpio_pd,   P8_38A(PIN_INPUT_PULLDOWN, 7) P8_38B(PIN_INPUT, 7))
	BONE_PIN(P8_38, uart,      P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 3))	/* uart5_rxd */

	/* P8_39 (AC26) PRG0_PRU1_GPO6 (gpio0_69) AC26_PRG0_PRU1_GPO6 */
	BONE_PIN(P8_39, default,   P8_39(PIN_INPUT, 7))
	BONE_PIN(P8_39, pruout,    P8_39(PIN_OUTPUT, 0))	/* prg0_pru1_gpo6 */
	BONE_PIN(P8_39, pruin,     P8_39(PIN_INPUT, 1))		/* prg0_pru1_gpi6 */
	BONE_PIN(P8_39, gpio,      P8_39(PIN_INPUT, 7))
	BONE_PIN(P8_39, gpio_pu,   P8_39(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_39, gpio_pd,   P8_39(PIN_INPUT_PULLDOWN, 7))

	/* P8_40 (AA24) PRG0_PRU1_GPO7 (gpio0_70) AA24_PRG0_PRU1_GPO7 */
	BONE_PIN(P8_40, default,   P8_40(PIN_INPUT, 7))
	BONE_PIN(P8_40, pruout,    P8_40(PIN_OUTPUT, 0))	/* prg0_pru1_gpo7 */
	BONE_PIN(P8_40, pruin,     P8_40(PIN_INPUT, 1))		/* prg0_pru1_gpi7 */
	BONE_PIN(P8_40, gpio,      P8_40(PIN_INPUT, 7))
	BONE_PIN(P8_40, gpio_pu,   P8_40(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_40, gpio_pd,   P8_40(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P8_40, uart,      P8_40(PIN_OUTPUT, 14))	/* uart2_txd */

	/* P8_41 (AD29) PRG0_PRU1_GPO4 (gpio0_67) AD29_PRG0_PRU1_GPO4 */
	BONE_PIN(P8_41, default,   P8_41(PIN_INPUT, 7))
	BONE_PIN(P8_41, pruout,    P8_41(PIN_OUTPUT, 0))	/* prg0_pru1_gpo4 */
	BONE_PIN(P8_41, pruin,     P8_41(PIN_INPUT, 1))		/* prg0_pru1_gpi4 */
	BONE_PIN(P8_41, gpio,      P8_41(PIN_INPUT, 7))
	BONE_PIN(P8_41, gpio_pu,   P8_41(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_41, gpio_pd,   P8_41(PIN_INPUT_PULLDOWN, 7))

	/* P8_42 (AB27) PRG0_PRU1_GPO5 (gpio0_68) AB27_SYS_BOOTMODE6 */
	BONE_PIN(P8_42, default,   P8_42(PIN_INPUT, 7))
	BONE_PIN(P8_42, pruout,    P8_42(PIN_OUTPUT, 0))	/* prg0_pru1_gpo5 */
	BONE_PIN(P8_42, pruin,     P8_42(PIN_INPUT, 1))		/* prg0_pru1_gpi5 */
	BONE_PIN(P8_42, gpio,      P8_42(PIN_INPUT, 7))
	BONE_PIN(P8_42, gpio_pu,   P8_42(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_42, gpio_pd,   P8_42(PIN_INPUT_PULLDOWN, 7))

	/* P8_43 (AD27) PRG0_PRU1_GPO2 (gpio0_65) AD27_PRG0_PRU1_GPO2 */
	BONE_PIN(P8_43, default,   P8_43(PIN_INPUT, 7))
	BONE_PIN(P8_43, pruout,    P8_43(PIN_OUTPUT, 0))	/* prg0_pru1_gpo2 */
	BONE_PIN(P8_43, pruin,     P8_43(PIN_INPUT, 1))		/* prg0_pru1_gpi2 */
	BONE_PIN(P8_43, gpio,      P8_43(PIN_INPUT, 7))
	BONE_PIN(P8_43, gpio_pu,   P8_43(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_43, gpio_pd,   P8_43(PIN_INPUT_PULLDOWN, 7))

	/* P8_44 (AC25) PRG0_PRU1_GPO3 (gpio0_66) AC25_PRG0_PRU1_GPO3 */
	BONE_PIN(P8_44, default,   P8_44(PIN_INPUT, 7))
	BONE_PIN(P8_44, pruout,    P8_44(PIN_OUTPUT, 0))	/* prg0_pru1_gpo3 */
	BONE_PIN(P8_44, pruin,     P8_44(PIN_INPUT, 1))		/* prg0_pru1_gpi3 */
	BONE_PIN(P8_44, gpio,      P8_44(PIN_INPUT, 7))
	BONE_PIN(P8_44, gpio_pu,   P8_44(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_44, gpio_pd,   P8_44(PIN_INPUT_PULLDOWN, 7))

	/* P8_45 (AG29) PRG0_PRU1_GPO16 (gpio0_79) AG29_PRG0_PRU1_GPO16 */
	BONE_PIN(P8_45, default,   P8_45(PIN_INPUT, 7))
	BONE_PIN(P8_45, pruout,    P8_45(PIN_OUTPUT, 0))	/* prg0_pru1_gpo16 */
	BONE_PIN(P8_45, pruin,     P8_45(PIN_INPUT, 1))		/* prg0_pru1_gpi16 */
	BONE_PIN(P8_45, gpio,      P8_45(PIN_INPUT, 7))
	BONE_PIN(P8_45, gpio_pu,   P8_45(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_45, gpio_pd,   P8_45(PIN_INPUT_PULLDOWN, 7))

	/* P8_46 (Y25) PRG0_PRU1_GPO17 (gpio0_80) Y25_SYS_BOOTMODE3 */
	BONE_PIN(P8_46, default,   P8_46(PIN_INPUT, 7))
	BONE_PIN(P8_46, pruout,    P8_46(PIN_OUTPUT, 0))	/* prg0_pru1_gpo17 */
	BONE_PIN(P8_46, pruin,     P8_46(PIN_INPUT, 1))		/* prg0_pru1_gpi17 */
	BONE_PIN(P8_46, gpio,      P8_46(PIN_INPUT, 7))
	BONE_PIN(P8_46, gpio_pu,   P8_46(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P8_46, gpio_pd,   P8_46(PIN_INPUT_PULLDOWN, 7))

	/* Full P9 header mode definitions */
	/* P9_01 - GND */
	/* P9_02 - GND */
	/* P9_03 - VOUT_3V3 */
	/* P9_04 - VOUT_3V3 */
	/* P9_05 - VIN */
	/* P9_06 - VIN */
	/* P9_07 - VOUT_SYS */
	/* P9_08 - VOUT_SYS */
	/* P9_09 - RESET# */
	/* P9_10 - POWER# */

	/* P9_11 (AC23) PRG1_PRU0_GPO0 (gpio0_1) AC23_UART0_RXD */
	BONE_PIN(P9_11, default,   P9_11(PIN_INPUT, 7))
	BONE_PIN(P9_11, pruout,    P9_11(PIN_OUTPUT, 0))	/* prg1_pru0_gpo0 */
	BONE_PIN(P9_11, pruin,     P9_11(PIN_INPUT, 1))		/* prg1_pru0_gpi0 */
	BONE_PIN(P9_11, gpio,      P9_11(PIN_INPUT, 7))
	BONE_PIN(P9_11, gpio_pu,   P9_11(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_11, gpio_pd,   P9_11(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_11, uart,      P9_11(PIN_INPUT, 14))	/* uart0_rxd */

	/* P9_12 (AE27) PRG0_PRU0_GPO2 (gpio0_45) AE27_MCASP0_ACLKR */
	BONE_PIN(P9_12, default,   P9_12(PIN_INPUT, 7))
	BONE_PIN(P9_12, pruout,    P9_12(PIN_OUTPUT, 0))	/* prg0_pru0_gpo2 */
	BONE_PIN(P9_12, pruin,     P9_12(PIN_INPUT, 1))		/* prg0_pru0_gpi2 */
	BONE_PIN(P9_12, gpio,      P9_12(PIN_INPUT, 7))
	BONE_PIN(P9_12, gpio_pu,   P9_12(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_12, gpio_pd,   P9_12(PIN_INPUT_PULLDOWN, 7))

	/* P9_13 (AG22) PRG1_PRU0_GPO1 (gpio0_2) AG22_UART0_TXD */
	BONE_PIN(P9_13, default,   P9_13(PIN_INPUT, 7))
	BONE_PIN(P9_13, pruout,    P9_13(PIN_OUTPUT, 0))	/* prg1_pru0_gpo1 */
	BONE_PIN(P9_13, pruin,     P9_13(PIN_INPUT, 1))		/* prg1_pru0_gpi1 */
	BONE_PIN(P9_13, gpio,      P9_13(PIN_INPUT, 7))
	BONE_PIN(P9_13, gpio_pu,   P9_13(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_13, gpio_pd,   P9_13(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_13, uart,      P9_13(PIN_OUTPUT, 14))	/* uart0_txd */

	/* P9_14 (U27) RGMII5_RD3 (gpio0_93) U27_EHRPWM2_A */
	BONE_PIN(P9_14, default,   P9_14(PIN_INPUT, 7))
	BONE_PIN(P9_14, gpio,      P9_14(PIN_INPUT, 7))
	BONE_PIN(P9_14, gpio_pu,   P9_14(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_14, gpio_pd,   P9_14(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_14, pwm,       P9_14(PIN_OUTPUT, 6))	/* ehrpwm2_a */

	/* P9_15 (AD25) PRG0_PRU0_GPO4 (gpio0_47) AD25_PRG0_PRU0_GPO4 */
	BONE_PIN(P9_15, default,   P9_15(PIN_INPUT, 7))
	BONE_PIN(P9_15, pruout,    P9_15(PIN_OUTPUT, 0))	/* prg0_pru0_gpo4 */
	BONE_PIN(P9_15, pruin,     P9_15(PIN_INPUT, 1))		/* prg0_pru0_gpi4 */
	BONE_PIN(P9_15, gpio,      P9_15(PIN_INPUT, 7))
	BONE_PIN(P9_15, gpio_pu,   P9_15(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_15, gpio_pd,   P9_15(PIN_INPUT_PULLDOWN, 7))

	/* P9_16 (U24) RGMII5_RD2 (gpio0_94) U24_EHRPWM2_B */
	BONE_PIN(P9_16, default,   P9_16(PIN_INPUT, 7))
	BONE_PIN(P9_16, pruout,    P9_16(PIN_OUTPUT, 0))
	BONE_PIN(P9_16, pruin,     P9_16(PIN_INPUT, 1))
	BONE_PIN(P9_16, gpio,      P9_16(PIN_INPUT, 7))
	BONE_PIN(P9_16, gpio_pu,   P9_16(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_16, gpio_pd,   P9_16(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_16, pwm,       P9_16(PIN_OUTPUT, 6))	/* ehrpwm2_b */

	/* P9_17 (AC21/AA3) PRG1_PRU1_GPO7/SPI0_D1 (gpio0_28/gpio0_115) AC21_AA3 */
	BONE_PIN(P9_17, default,   P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT, 7))
	BONE_PIN(P9_17, pruout,    P9_17A(PIN_OUTPUT, 0) P9_17B(PIN_INPUT, 7))	/* prg1_pru1_gpo7 */
	BONE_PIN(P9_17, pruin,     P9_17A(PIN_INPUT, 1) P9_17B(PIN_INPUT, 7))	/* prg1_pru1_gpi7 */
	BONE_PIN(P9_17, gpio,      P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT, 7))	/* gpio0_28 */
	BONE_PIN(P9_17, gpio_pu,   P9_17A(PIN_INPUT_PULLUP, 7) P9_17B(PIN_INPUT, 7))
	BONE_PIN(P9_17, gpio_pd,   P9_17A(PIN_INPUT_PULLDOWN, 7) P9_17B(PIN_INPUT, 7))
	BONE_PIN(P9_17, i2c,       P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT_PULLUP, 2))	/* i2c6_scl */
	BONE_PIN(P9_17, spi,       P9_17A(PIN_OUTPUT, 4) P9_17B(PIN_INPUT, 7))	/* spi6_cs0 */

	/* P9_18 (AH22/Y2) PRG1_PRU1_GPO19/SPI1_D1 (gpio0_40/gpio0_120) AH22_Y2 */
	BONE_PIN(P9_18, default,   P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT, 7))
	BONE_PIN(P9_18, pruout,    P9_18A(PIN_OUTPUT, 0) P9_18B(PIN_INPUT, 7))	/* prg1_pru1_gpo19 */
	BONE_PIN(P9_18, pruin,     P9_18A(PIN_INPUT, 1) P9_18B(PIN_INPUT, 7))	/* prg1_pru1_gpi19 */
	BONE_PIN(P9_18, gpio,      P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT, 7))	/* gpio0_40 */
	BONE_PIN(P9_18, gpio_pu,   P9_18A(PIN_INPUT_PULLUP, 7) P9_18B(PIN_INPUT, 7))
	BONE_PIN(P9_18, gpio_pd,   P9_18A(PIN_INPUT_PULLDOWN, 7) P9_18B(PIN_INPUT, 7))
	BONE_PIN(P9_18, i2c,       P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT_PULLUP, 2))	/* i2c6_sda */
	BONE_PIN(P9_18, spi,       P9_18A(PIN_INPUT, 4) P9_18B(PIN_INPUT, 7))	/* spi6_d1 (tested PIN_INPUT) */

	/* P9_19 (W5/AF29) MCAN0_RX/PRG0_PRU1_GPO15 (gpio1_1/gpio0_78) W5_AF29 */
	BONE_PIN(P9_19, default,   P9_19A(PIN_INPUT, 7) P9_19B(PIN_INPUT, 7))
	BONE_PIN(P9_19, pruout,    P9_19A(PIN_INPUT, 7) P9_19B(PIN_OUTPUT, 0))	/* prg0_pru1_gpo15 */
	BONE_PIN(P9_19, pruin,     P9_19A(PIN_INPUT, 7) P9_19B(PIN_INPUT, 1))	/* prg0_pru1_gpi15 */
	BONE_PIN(P9_19, can,       P9_19A(PIN_INPUT, 0) P9_19B(PIN_INPUT, 7))	/* mcan0_rx */
	BONE_PIN(P9_19, gpio,      P9_19A(PIN_INPUT, 7) P9_19B(PIN_INPUT, 7))	/* gpio1_1 */
	BONE_PIN(P9_19, gpio_pu,   P9_19A(PIN_INPUT_PULLUP, 7) P9_19B(PIN_INPUT, 7))
	BONE_PIN(P9_19, gpio_pd,   P9_19A(PIN_INPUT_PULLDOWN, 7) P9_19B(PIN_INPUT, 7))
	BONE_PIN(P9_19, i2c,       P9_19A(PIN_INPUT_PULLUP, 4) P9_19B(PIN_INPUT, 7))	/* i2c2_scl */

	/* P9_20 (W6/AE25) MCAN0_TX/PRG0_PRU1_GPO14 (gpio1_2/gpio0_77) W6_AE25 */
	BONE_PIN(P9_20, default,   P9_20A(PIN_INPUT, 7) P9_20B(PIN_INPUT, 7))
	BONE_PIN(P9_20, pruout,    P9_20A(PIN_INPUT, 7) P9_20B(PIN_OUTPUT, 0))	/* prg0_pru1_gpo14 */
	BONE_PIN(P9_20, pruin,     P9_20A(PIN_INPUT, 7) P9_20B(PIN_INPUT, 1))	/* prg0_pru1_gpi14 */
	BONE_PIN(P9_20, can,       P9_20A(PIN_OUTPUT, 0) P9_20B(PIN_INPUT, 7))	/* mcan0_tx */
	BONE_PIN(P9_20, gpio,      P9_20A(PIN_INPUT, 7) P9_20B(PIN_INPUT, 7))	/* gpio1_2 */
	BONE_PIN(P9_20, gpio_pu,   P9_20A(PIN_INPUT_PULLUP, 7) P9_20B(PIN_INPUT, 7))
	BONE_PIN(P9_20, gpio_pd,   P9_20A(PIN_INPUT_PULLDOWN, 7) P9_20B(PIN_INPUT, 7))
	BONE_PIN(P9_20, i2c,       P9_20A(PIN_INPUT_PULLUP, 4) P9_20B(PIN_INPUT, 7))	/* i2c2_sda */

	/* P9_21 (AJ22/U28) PRG1_PRU1_GPO18/RGMII5_TD0 (gpio0_39/gpio0_90) AJ22_U28 */
	BONE_PIN(P9_21, default,   P9_21A(PIN_INPUT, 7) P9_21B(PIN_INPUT, 7))
	BONE_PIN(P9_21, pruout,    P9_21A(PIN_OUTPUT, 0) P9_21B(PIN_INPUT, 7))	/* prg1_pru1_gpo18 */
	BONE_PIN(P9_21, pruin,     P9_21A(PIN_INPUT, 1) P9_21B(PIN_INPUT, 7))	/* prg1_pru1_gpi18 */
	BONE_PIN(P9_21, gpio,      P9_21A(PIN_INPUT, 7) P9_21B(PIN_INPUT, 7))	/* gpio0_39 */
	BONE_PIN(P9_21, gpio_pu,   P9_21A(PIN_INPUT_PULLUP, 7) P9_21B(PIN_INPUT, 7))
	BONE_PIN(P9_21, gpio_pd,   P9_21A(PIN_INPUT_PULLDOWN, 7) P9_21B(PIN_INPUT, 7))
	BONE_PIN(P9_21, pwm,       P9_21A(PIN_INPUT, 7) P9_21B(PIN_OUTPUT, 6))	/* ehrpwm1_a */
	BONE_PIN(P9_21, spi,       P9_21A(PIN_OUTPUT, 4) P9_21B(PIN_INPUT, 7))	/* spi6_d0 */

	/* P9_22 (AC22/U29) PRG1_PRU1_GPO17/RGMII5_TXC (gpio0_38/gpio0_91) AC22_U29 */
	BONE_PIN(P9_22, default,   P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT, 7))
	BONE_PIN(P9_22, pruout,    P9_22A(PIN_OUTPUT, 0) P9_22B(PIN_INPUT, 7))	/* prg1_pru1_gpo17 */
	BONE_PIN(P9_22, pruin,     P9_22A(PIN_INPUT, 1) P9_22B(PIN_INPUT, 7))	/* prg1_pru1_gpi17 */
	BONE_PIN(P9_22, gpio,      P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT, 7))	/* gpio0_38 */
	BONE_PIN(P9_22, gpio_pu,   P9_22A(PIN_INPUT_PULLUP, 7) P9_22B(PIN_INPUT, 7))
	BONE_PIN(P9_22, gpio_pd,   P9_22A(PIN_INPUT_PULLDOWN, 7) P9_22B(PIN_INPUT, 7))
	BONE_PIN(P9_22, i2c,       P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT_PULLUP, 2))	/* i2c6_scl */
	BONE_PIN(P9_22, pwm,       P9_22A(PIN_INPUT, 7) P9_22B(PIN_OUTPUT, 6))	/* ehrpwm1_b */
	BONE_PIN(P9_22, spi,       P9_22A(PIN_OUTPUT, 4) P9_22B(PIN_INPUT, 7))	/* spi6_clk */

	/* P9_23 (AG20) PRG1_PRU0_GPO9 (gpio0_10) AG20_SPI6_CS1 */
	BONE_PIN(P9_23, default,   P9_23(PIN_INPUT, 7))
	BONE_PIN(P9_23, pruout,    P9_23(PIN_OUTPUT, 0))	/* prg1_pru0_gpo9 */
	BONE_PIN(P9_23, pruin,     P9_23(PIN_INPUT, 1))		/* prg1_pru0_gpi9 */
	BONE_PIN(P9_23, gpio,      P9_23(PIN_INPUT, 7))
	BONE_PIN(P9_23, gpio_pu,   P9_23(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_23, gpio_pd,   P9_23(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_23, spi,       P9_23(PIN_OUTPUT, 4))	/* spi6_cs1 */

	/* P9_24 (Y5/AJ24) SPI1_D0/PRG1_PRU0_GPO12 (gpio0_119/gpio0_13) Y5_AJ24 */
	BONE_PIN(P9_24, default,   P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 7))
	BONE_PIN(P9_24, pruout,    P9_24A(PIN_INPUT, 7) P9_24B(PIN_OUTPUT, 0))	/* prg1_pru0_gpo12 */
	BONE_PIN(P9_24, pruin,     P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 1))	/* prg1_pru0_gpi12 */
	BONE_PIN(P9_24, can,       P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 6) )	/* mcan4_rx */
	BONE_PIN(P9_24, gpio,      P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 7))	/* gpio0_119 */
	BONE_PIN(P9_24, gpio_pu,   P9_24A(PIN_INPUT_PULLUP, 7) P9_24B(PIN_INPUT, 7))
	BONE_PIN(P9_24, gpio_pd,   P9_24A(PIN_INPUT_PULLDOWN, 7) P9_24B(PIN_INPUT, 7))
	BONE_PIN(P9_24, i2c,       P9_24A(PIN_INPUT_PULLUP, 2) P9_24B(PIN_INPUT, 7))	/* i2c4_scl */
	BONE_PIN(P9_24, uart,      P9_24A(PIN_OUTPUT, 3) P9_24B(PIN_INPUT, 7))	/* uart2_txd */

	/* P9_25 (AC4/W26) UART1_CTSn/RGMII6_RXC (gpio0_127/gpio0_104) AC4_W26 */
	BONE_PIN(P9_25, default,   P9_25A(PIN_INPUT, 7) P9_25B(PIN_INPUT, 7))
	BONE_PIN(P9_25, gpio,      P9_25A(PIN_INPUT, 7) P9_25B(PIN_INPUT, 7))	/* gpio0_127 */
	BONE_PIN(P9_25, gpio_pu,   P9_25A(PIN_INPUT_PULLUP, 7) P9_25B(PIN_INPUT, 7))
	BONE_PIN(P9_25, gpio_pd,   P9_25A(PIN_INPUT_PULLDOWN, 7) P9_25B(PIN_INPUT, 7))
	BONE_PIN(P9_25, pwm,       P9_25A(PIN_INPUT, 7) P9_25B(PIN_OUTPUT, 6))	/* ehrpwm4_b */
	BONE_PIN(P9_25, qep,       P9_25A(PIN_INPUT, 5) P9_25B(PIN_INPUT, 7))	/* eqep0_s */

	/* P9_26 (Y1/AF24) SPI1_CLK/PRG1_PRU0_GPO11 (gpio0_118/gpio0_12) Y1_AF24 */
	BONE_PIN(P9_26, default,   P9_26A(PIN_INPUT, 7) P9_26B(PIN_INPUT, 7))
	BONE_PIN(P9_26, pruout,    P9_26A(PIN_INPUT, 7) P9_26B(PIN_OUTPUT, 0))	/* prg1_pru0_gpo11 */
	BONE_PIN(P9_26, pruin,     P9_26A(PIN_INPUT, 7) P9_26B(PIN_INPUT, 1))	/* prg1_pru0_gpi11 */
	BONE_PIN(P9_26, can,       P9_26A(PIN_INPUT, 7) P9_26B(PIN_OUTPUT, 6) )	/* mcan4_tx */
	BONE_PIN(P9_26, gpio,      P9_26A(PIN_INPUT, 7) P9_26B(PIN_INPUT, 7))	/* gpio0_118 */
	BONE_PIN(P9_26, gpio_pu,   P9_26A(PIN_INPUT_PULLUP, 7) P9_26B(PIN_INPUT, 7))
	BONE_PIN(P9_26, gpio_pd,   P9_26A(PIN_INPUT_PULLDOWN, 7) P9_26B(PIN_INPUT, 7))
	BONE_PIN(P9_26, i2c,       P9_26A(PIN_INPUT_PULLUP, 2) P9_26B(PIN_INPUT, 7))	/* i2c4_sda */
	BONE_PIN(P9_26, uart,      P9_26A(PIN_INPUT, 3) P9_26B(PIN_INPUT, 7))	/* uart2_rxd */

	/* P9_27 (AD26/AB1) PRG0_PRU0_GPO3/UART0_RTSn (gpio0_46/gpio0_124) AD26_AB1 */
	BONE_PIN(P9_27, default,   P9_27A(PIN_INPUT, 7) P9_27B(PIN_INPUT, 7))
	BONE_PIN(P9_27, pruout,    P9_27A(PIN_OUTPUT, 0) P9_27B(PIN_INPUT, 7))	/* prg0_pru0_gpo3 */
	BONE_PIN(P9_27, pruin,     P9_27A(PIN_INPUT, 1) P9_27B(PIN_INPUT, 7))	/* prg0_pru0_gpi3 */
	BONE_PIN(P9_27, gpio,      P9_27A(PIN_INPUT, 7) P9_27B(PIN_INPUT, 7))	/* gpio0_46 */
	BONE_PIN(P9_27, gpio_pu,   P9_27A(PIN_INPUT_PULLUP, 7) P9_27B(PIN_INPUT, 7))
	BONE_PIN(P9_27, gpio_pd,   P9_27A(PIN_INPUT_PULLDOWN, 7) P9_27B(PIN_INPUT, 7))
	BONE_PIN(P9_27, qep,       P9_27A(PIN_INPUT, 7) P9_27B(PIN_INPUT, 5))	/* eqep0_b */

	/* P9_28 (U2/AF28) ECAP0_IN_APWM_OUT/PRG0_PRU0_GPO0 (gpio1_11/gpio0_43) U2_AF28 */
	BONE_PIN(P9_28, default,   P9_28A(PIN_INPUT, 7) P9_28B(PIN_INPUT, 7))
	BONE_PIN(P9_28, pruout,    P9_28A(PIN_INPUT, 7) P9_28B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo0 */
	BONE_PIN(P9_28, pruin,     P9_28A(PIN_INPUT, 7) P9_28B(PIN_INPUT, 1))	/* prg0_pru0_gpi0 */
	BONE_PIN(P9_28, gpio,      P9_28A(PIN_INPUT, 7) P9_28B(PIN_INPUT, 7))	/* gpio1_11 */
	BONE_PIN(P9_28, gpio_pu,   P9_28A(PIN_INPUT_PULLUP, 7) P9_28B(PIN_INPUT, 7))
	BONE_PIN(P9_28, gpio_pd,   P9_28A(PIN_INPUT_PULLDOWN, 7) P9_28B(PIN_INPUT, 7))
	BONE_PIN(P9_28, spi,       P9_28A(PIN_OUTPUT, 6) P9_28B(PIN_INPUT, 7))	/* spi7_cs0 */

	/* P9_29 (V5/AB25) TIMER_IO1/PRG0_PRU0_GPO10 (gpio1_14/gpio0_53) V5_AB25 */
	BONE_PIN(P9_29, default,   P9_29A(PIN_INPUT, 7) P9_29B(PIN_INPUT, 7))
	BONE_PIN(P9_29, pruout,    P9_29A(PIN_INPUT, 7) P9_29B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo10 */
	BONE_PIN(P9_29, pruin,     P9_29A(PIN_INPUT, 7) P9_29B(PIN_INPUT, 1))	/* prg0_pru0_gpi10 */
	BONE_PIN(P9_29, gpio,      P9_29A(PIN_INPUT, 7) P9_29B(PIN_INPUT, 7))	/* gpio1_14 */
	BONE_PIN(P9_29, gpio_pu,   P9_29A(PIN_INPUT_PULLUP, 7) P9_29B(PIN_INPUT, 7))
	BONE_PIN(P9_29, gpio_pd,   P9_29A(PIN_INPUT_PULLDOWN, 7) P9_29B(PIN_INPUT, 7))
	/* https://forum.beagleboard.org/t/bbai-64-bone-spi1-0-overlay-development-and-debug/34113/10 */
	BONE_PIN(P9_29, spi,       P9_29A(PIN_INPUT, 6) P9_29B(PIN_INPUT, 7))   /* spi7_d1 (tested PIN_INPUT) */

	/* P9_30 (V6/AE28) TIMER_IO0/PRG0_PRU0_GPO1 (gpio1_13/gpio0_44) V6_AE28 */
	BONE_PIN(P9_30, default,   P9_30A(PIN_INPUT, 7) P9_30B(PIN_INPUT, 7))
	BONE_PIN(P9_30, pruout,    P9_30A(PIN_INPUT, 7) P9_30B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo1 */
	BONE_PIN(P9_30, pruin,     P9_30A(PIN_INPUT, 7) P9_30B(PIN_INPUT, 1))	/* prg0_pru0_gpi1 */
	BONE_PIN(P9_30, gpio,      P9_30A(PIN_INPUT, 7) P9_30B(PIN_INPUT, 7))	/* gpio1_13 */
	BONE_PIN(P9_30, gpio_pu,   P9_30A(PIN_INPUT_PULLUP, 7) P9_30B(PIN_INPUT, 7))
	BONE_PIN(P9_30, gpio_pd,   P9_30A(PIN_INPUT_PULLDOWN, 7) P9_30B(PIN_INPUT, 7))
	BONE_PIN(P9_30, spi,       P9_30A(PIN_OUTPUT, 6) P9_30B(PIN_INPUT, 7))	/* spi7_d0 */

	/* P9_31 (U3/AB26) EXT_REFCLK1/PRG0_PRU0_GPO9 (gpio1_12/gpio0_52) U3_AB26 */
	BONE_PIN(P9_31, default,   P9_31A(PIN_INPUT, 7) P9_31B(PIN_INPUT, 7))
	BONE_PIN(P9_31, pruout,    P9_31A(PIN_INPUT, 7) P9_31B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo9 */
	BONE_PIN(P9_31, pruin,     P9_31A(PIN_INPUT, 7) P9_31B(PIN_INPUT, 1))	/* prg0_pru0_gpi9 */
	BONE_PIN(P9_31, gpio,      P9_31A(PIN_INPUT, 7) P9_31B(PIN_INPUT, 7))	/* gpio1_12 */
	BONE_PIN(P9_31, gpio_pu,   P9_31A(PIN_INPUT_PULLUP, 7) P9_31B(PIN_INPUT, 7))
	BONE_PIN(P9_31, gpio_pd,   P9_31A(PIN_INPUT_PULLDOWN, 7) P9_31B(PIN_INPUT, 7))
	BONE_PIN(P9_31, spi,       P9_31A(PIN_OUTPUT, 6) P9_31B(PIN_INPUT, 7))	/* spi7_clk */

	/* P9_32 - ADC_REF_OUT */

	/* P9_33 (K24/AC28) MCU_ADC0_AIN4/PRG0_PRU0_GPO7 (gpio0_50) K24_AC28 */
	BONE_PIN(P9_33, default,   P9_33B(PIN_INPUT, 7))
	BONE_PIN(P9_33, pruout,    P9_33B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo7 */
	BONE_PIN(P9_33, pruin,     P9_33B(PIN_INPUT, 1))	/* prg0_pru0_gpi7 */
	BONE_PIN(P9_33, gpio,      P9_33B(PIN_INPUT, 7))
	BONE_PIN(P9_33, gpio_pu,   P9_33B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_33, gpio_pd,   P9_33B(PIN_INPUT_PULLDOWN, 7))

	/* P9_34 - ADC_GND */

	/* P9_35 (K29/AH27) MCU_ADC0_AIN6/PRG0_PRU0_GPO12 (gpio0_55) K29_AH27 */
	BONE_PIN(P9_35, default,   P9_35B(PIN_INPUT, 7))
	BONE_PIN(P9_35, pruout,    P9_35B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo12 */
	BONE_PIN(P9_35, pruin,     P9_35B(PIN_INPUT, 1))	/* prg0_pru0_gpi12 */
	BONE_PIN(P9_35, gpio,      P9_35B(PIN_INPUT, 7))
	BONE_PIN(P9_35, gpio_pu,   P9_35B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_35, gpio_pd,   P9_35B(PIN_INPUT_PULLDOWN, 7))

	/* P9_36 (K27/AH29) MCU_ADC0_AIN5/PRG0_PRU0_GPO13 (gpio0_56) K27_AH29 */
	BONE_PIN(P9_36, default,   P9_36B(PIN_INPUT, 7))
	BONE_PIN(P9_36, pruout,    P9_36B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo13 */
	BONE_PIN(P9_36, pruin,     P9_36B(PIN_INPUT, 1))	/* prg0_pru0_gpi13 */
	BONE_PIN(P9_36, gpio,      P9_36B(PIN_INPUT, 7))
	BONE_PIN(P9_36, gpio_pu,   P9_36B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_36, gpio_pd,   P9_36B(PIN_INPUT_PULLDOWN, 7))

	/* P9_37 (K28/AG28) MCU_ADC0_AIN2/PRG0_PRU0_GPO14 (gpio0_57) K28_AG28 */
	BONE_PIN(P9_37, default,   P9_37B(PIN_INPUT, 7))
	BONE_PIN(P9_37, pruout,    P9_37B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo14 */
	BONE_PIN(P9_37, pruin,     P9_37B(PIN_INPUT, 1))	/* prg0_pru0_gpi14 */
	BONE_PIN(P9_37, gpio,      P9_37B(PIN_INPUT, 7))
	BONE_PIN(P9_37, gpio_pu,   P9_37B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_37, gpio_pd,   P9_37B(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_37, uart,      P9_37A(PIN_INPUT, 7) P9_37B(PIN_INPUT, 8))	/* uart4_rxd */

	/* P9_38 (L28/AG27) MCU_ADC0_AIN3/PRG0_PRU0_GPO15 (gpio0_58) L28_AG27 */
	BONE_PIN(P9_38, default,   P9_38B(PIN_INPUT, 7))
	BONE_PIN(P9_38, pruout,    P9_38B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo15 */
	BONE_PIN(P9_38, pruin,     P9_38B(PIN_INPUT, 1))	/* prg0_pru0_gpi15 */
	BONE_PIN(P9_38, gpio,      P9_38B(PIN_INPUT, 7))
	BONE_PIN(P9_38, gpio_pu,   P9_38B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_38, gpio_pd,   P9_38B(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_38, uart,      P9_38A(PIN_INPUT, 7) P9_38B(PIN_OUTPUT, 8))	/* uart4_txd */

	/* P9_39 (K25/AJ28) MCU_ADC0_AIN0/PRG0_PRU0_GPO11 (gpio0_54) K25_AJ28 */
	BONE_PIN(P9_39, default,   P9_39B(PIN_INPUT, 7))
	BONE_PIN(P9_39, pruout,    P9_39B(PIN_OUTPUT, 0))	/* prg0_pru0_gpo11 */
	BONE_PIN(P9_39, pruin,     P9_39B(PIN_INPUT, 1))	/* prg0_pru0_gpi11 */
	BONE_PIN(P9_39, gpio,      P9_39B(PIN_INPUT, 7))
	BONE_PIN(P9_39, gpio_pu,   P9_39B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_39, gpio_pd,   P9_39B(PIN_INPUT_PULLDOWN, 7))

	/* P9_40 (K26/AA26) MCU_ADC0_AIN1/PRG0_PRU1_GPO18 (gpio0_81) K26_AA26 */
	BONE_PIN(P9_40, default,   P9_40B(PIN_INPUT, 7))
	BONE_PIN(P9_40, pruout,    P9_40B(PIN_OUTPUT, 0))	/* prg0_pru1_gpo18 */
	BONE_PIN(P9_40, pruin,     P9_40B(PIN_INPUT, 1))	/* prg0_pru1_gpi18 */
	BONE_PIN(P9_40, gpio,      P9_40B(PIN_INPUT, 7))
	BONE_PIN(P9_40, gpio_pu,   P9_40B(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_40, gpio_pd,   P9_40B(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_40, uart,      P9_40B(PIN_INPUT, 14))	/* uart2_rxd */

	/* P9_41 (AD5) UART1_RTSn (gpio1_0) AD5_EQEP0_I */
	BONE_PIN(P9_41, default,   P9_41(PIN_INPUT, 7))
	BONE_PIN(P9_41, pruout,    P9_41(PIN_OUTPUT, 0))
	BONE_PIN(P9_41, pruin,     P9_41(PIN_INPUT, 1))
	BONE_PIN(P9_41, gpio,      P9_41(PIN_INPUT, 7))
	BONE_PIN(P9_41, gpio_pu,   P9_41(PIN_INPUT_PULLUP, 7))
	BONE_PIN(P9_41, gpio_pd,   P9_41(PIN_INPUT_PULLDOWN, 7))
	BONE_PIN(P9_41, qep,       P9_41(PIN_INPUT, 5))	/* eqep0_i */

	/* P9_42 (AC2/AJ21) UART0_CTSn/PRG1_PRU0_GPO17 (gpio0_123/gpio0_18) AC2_AJ21 */
	BONE_PIN(P9_42, default,   P9_42A(PIN_INPUT, 7) P9_42B(PIN_INPUT, 7))
	BONE_PIN(P9_42, pruout,    P9_42A(PIN_INPUT, 7) P9_42B(PIN_OUTPUT, 0))	/* prg1_pru0_gpo17 */
	BONE_PIN(P9_42, pruin,     P9_42A(PIN_INPUT, 7) P9_42B(PIN_INPUT, 1))	/* prg1_pru0_gpi17 */
	BONE_PIN(P9_42, can,       P9_42A(PIN_INPUT, 7) P9_42B(PIN_OUTPUT, 6) )	/* mcan5_tx */
	BONE_PIN(P9_42, gpio,      P9_42A(PIN_INPUT, 7) P9_42B(PIN_INPUT, 7))	/* gpio0_123 */
	BONE_PIN(P9_42, gpio_pu,   P9_42A(PIN_INPUT_PULLUP, 7) P9_42B(PIN_INPUT, 7))
	BONE_PIN(P9_42, gpio_pd,   P9_42A(PIN_INPUT_PULLDOWN, 7) P9_42B(PIN_INPUT, 7))
	BONE_PIN(P9_42, qep,       P9_42A(PIN_INPUT, 5) P9_42B(PIN_INPUT, 7))	/* eqep0_a */

	/* P9_43 - GND */
	/* P9_44 - GND */
	/* P9_45 - GND */
	/* P9_46 - GND */

	// Additional Pinmux for UART6 (used by BONE-UART4)
	uart6_pins_default: uart6-pins-default {
		pinctrl-single,pins = <
			P9_14(PIN_INPUT, 3)   /* UART6 RX */
			P9_16(PIN_OUTPUT, 3)  /* UART6 TX */
		>;
	};

	p8_19_gpio_pin: pinmux_p8_19_gpio_pin {
			pinctrl-single,pins = <
					P8_19(PIN_INPUT, 7)
			>;
	};

	p8_33_gpio_pin: pinmux_p8_33_gpio_pin {
			pinctrl-single,pins = <
					P8_33A(PIN_INPUT, 7)
			>;
	};
};

/*
 * --------------------------------------------------
 * This file maps the UART, CAN, GPIO peripherals to their respective hardware resources,
 * such as pins, power domains, and symlink aliases.
 *
 * Structure of Configuration:
 * ---------------------------
 * <label>: &<reference_node> {
 *     pinctrl-names: Defines the pinctrl state (e.g., "default").
 *     pinctrl-0:     Specifies the pinmux settings for this peripheral.
 *     symlink:       Defines the alias used for this peripheral (e.g., bone/uart/X).
 *     power-domains: Specifies the power domain for the UART peripheral.
 *     status:        Enables ("okay") or disables ("disabled") the peripheral.
 * };
 *
 * Notes:
 * - Labels (e.g., bone_uart_0, bone_uart_1) are logical names used for referencing.
 * - References (e.g., &main_uart0, &main_uart2) point to the base hardware definitions in the SoC-level .dtsi file as defined in: k3-j721e-main.dtsi
 */

// ========================================
// UART configuration for BeagleBone AI-64
// ========================================

/* BeagleBoard AI64 UART Port Mapping Table as defined here: https://docs.beagleboard.org/boards/capes/cape-interface-spec.html#id48
 *
 * +-----------------+-------------+---------+---------+---------+---------------------+
 * | Bone Bus        | DT Symbol   | AI-64   | TX      | RX      | Overlay             |
 * +-----------------+-------------+---------+---------+---------+---------------------+
 * | /dev/bone/uart/0| bone_uart_0 | MAIN_UART0 | P9.24 | P9.26  | Console Debug       |
 * | /dev/bone/uart/1| bone_uart_1 | MAIN_UART2 | P9.24 | P9.26  | BONE-UART1          |
 * | /dev/bone/uart/2| bone_uart_2 | n/a       | P9.21 | P9.22  | BONE-UART2          |
 * | /dev/bone/uart/3| bone_uart_3 | n/a       | P9.42 | n/a    | BONE-UART3          |
 * | /dev/bone/uart/4| bone_uart_4 | MAIN_UART0| P9.13 | P9.11  | BONE-UART4          |
 * | /dev/bone/uart/5| bone_uart_5 | MAIN_UART5| P8.37 | P8.38  | BONE-UART5          |
 * | /dev/bone/uart/6| bone_uart_6 | MAIN_UART8| P8.29 | P8.30  | BONE-UART6          |
 * | /dev/bone/uart/7| bone_uart_7 | MAIN_UART2| P8.34 | P8.22  | BONE-UART7          |
 * +-----------------+-------------+---------+---------+---------+---------------------+
 *
 * Notes:
 * - The important fields are the AI-64, TX, and RX columns which map to the physical pins on the board and cannot be renamed or changed
 */

/* UART 1: Peripheral on Pins P9_24 (TX) and P9_26 (RX) */
bone_uart_1: &main_uart2 { 
    /* 
     * Description: 
     * 
     * Notes:
     * - UART is enabled in BONE-UART1.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P9_24_uart_pin /* TX */
        &P9_26_uart_pin /* RX */
    >;
    symlink = "bone/uart/1";
    status = "disabled";
};

/* UART 2: Peripheral on Pins P8_37 (TX) and P8_38 (RX) */
bone_uart_2: &main_uart5 {
    /* 
     * Description:
     * 
     * Notes:
     * - UART is enabled in BONE-UART2.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P8_37_uart_pin /* TX */
        &P8_38_uart_pin /* RX */
    >;
    symlink = "bone/uart/2";
    status = "disabled";
};

/* UART 3: Peripheral on Pins P8_29 (TX) and P8_28 (RX) */
bone_uart_3: &main_uart8 {
    /* 
     * Description:
     * 
     * Notes:
     * - UART is enabled in BONE-UART3.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P8_29_uart_pin /* TX */
        &P8_28_uart_pin /* RX */
    >;
    symlink = "bone/uart/3";
    status = "disabled";
};

/* UART4 Configuration */
bone_uart_4: &main_uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart6_pins_default>;
	symlink = "bone/uart/4";
	status = "disabled"; // Default disabled; enabled via overlay
};

// ========================================
// CAN configuration for BeagleBone AI-64
// ========================================

/* BeagleBoard AI64 CAN Port Mapping Table as defined here: https://docs.beagleboard.org/boards/capes/cape-interface-spec.html#id50
 *
 * +------------------+---------+---------+---------------------+
 * | Bone Bus         | AI-64   | TX      | RX      | Overlay   |
 * +------------------+---------+---------+---------+-----------+
 * | /dev/bone/can/0  | MAIN_MCAN0 | P9.20 | P9.19  | BONE-CAN0 |
 * | /dev/bone/can/1  | MAIN_MCAN4 | P9.26 | P9.24  | BONE-CAN1 |
 * | /dev/bone/can/2  | MAIN_MCAN5 | P8.08 | P8.07  | BONE-CAN2 |
 * | /dev/bone/can/3  | MAIN_MCAN6 | P8.10 | P8.09  | BONE-CAN3 |
 * | /dev/bone/can/4  | MAIN_MCAN7 | P8.05 | P8.06  | BONE-CAN4 |
 * +------------------+---------+---------+---------+-----------+
 *
 * Notes:
 * - The important fields are the AI-64, TX, and RX columns which map to the physical pins on the board and cannot be renamed or changed
 */

/* CAN 1: Peripheral on Pins P8_10 (TX) and P8_09 (RX) */
bone_can_1: &main_mcan6 { 
    /* 
     * Description: 
     * 
     * Notes:
     * - CAN is enabled in BONE-CAN1.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P8_10_can_pin /* TX */
        &P8_09_can_pin /* RX */
    >;
    symlink = "bone/can/1";
    status = "disabled";
};

/* CAN 2: Peripheral on Pins P8_08 (TX) and P8_07 (RX) */
bone_can_2: &main_mcan5 { 
    /* 
     * Description: 
     * 
     * Notes:
     * - CAN is enabled in BONE-CAN2.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P8_08_can_pin /* TX */
        &P8_07_can_pin /* RX */
    >;
    symlink = "bone/can/2";
    status = "disabled";
};

/* CAN 3: Peripheral on Pins P9_20 (TX) and P9_19 (RX) */
bone_can_3: &main_mcan0 { 
    /* 
     * Description: 
     * 
     * Notes:
     * - CAN is enabled in BONE-CAN3.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P9_20_can_pin /* TX */
        &P9_19_can_pin /* RX */
    >;
    symlink = "bone/can/3";
    status = "disabled";
};

/* CAN 4: Peripheral on Pins P8_05 (TX) and P8_06 (RX) */
bone_can_4: &main_mcan7 { 
    /* 
     * Description: 
     * 
     * Notes:
     * - CAN is enabled in BONE-CAN4.dts
     */
    pinctrl-names = "default";
    pinctrl-0 = <
        &P8_05_can_pin /* TX */
        &P8_06_can_pin /* RX */
    >;
    symlink = "bone/can/4";
    status = "disabled";
};


 // ========================================
// GPIO configuration for BeagleBone AI-64
// ========================================

/* BeagleBoard AI-64 GPIO Mapping Table as defined here:
 * https://docs.beagleboard.org/boards/capes/cape-interface-spec.html#digital-gpio
 *
 * +----------------------+-----------+------------+
 * | SYSFS link           | AI-64     | Header Pin |
 * +----------------------+-----------+------------+
 * | /sys/class/leds/P8_19| gpio0_88  | P8.19      |
 * | /sys/class/leds/P8_33| gpio0_25  | P8.33      |
 * +----------------------+-----------+------------+
 *
 * Notes:
 * - The important fields are the AI-64 values, which map to the physical pins 
 *   on the board and cannot be renamed or changed.
 */

&main_gpio0 {
		bone_gpio_1: bone-gpio-1 {
				compatible = "mytra,raw-gpio-pin";
				pinctrl-names = "default";
				pinctrl-0 = <&p8_19_gpio_pin>;
				gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>;
				symlink = "bone/gpio/1";
				status = "disabled";
		};

		bone_gpio_2: bone-gpio-2 {
				compatible = "mytra,raw-gpio-pin";
				pinctrl-names = "default";
				pinctrl-0 = <&p8_33_gpio_pin>;
				gpios = <&main_gpio0 25 GPIO_ACTIVE_HIGH>;
				symlink = "bone/gpio/2";
				status = "disabled";
		};
};

Our device tree change:

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
 *
 * Combined overlay to enable UART1, UART2, UART3, and UART4 on BeagleBone AI-64
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/board/k3-j721e-bone-pins.h>

/*
 * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
 */
&{/chosen} {
    overlays {
        BONE-UART1.kernel = __TIMESTAMP__;
        BONE-UART2.kernel = __TIMESTAMP__;
        BONE-UART3.kernel = __TIMESTAMP__;
        BONE-UART4.kernel = __TIMESTAMP__;
    };
};

/*
 * Enable UART1 Peripheral as defined in: k3-j721e-beagleboneai64-bone-buses.dtsi
 */
&bone_uart_1 {
    status = "okay"; // Enable UART1
};

/*
 * Enable UART2 Peripheral as defined in: k3-j721e-beagleboneai64-bone-buses.dtsi
 */
&bone_uart_2 {
    status = "okay"; // Enable UART2
};

/*
 * Enable UART3 Peripheral as defined in: k3-j721e-beagleboneai64-bone-buses.dtsi
 */
&bone_uart_3 {
    status = "okay"; // Enable UART3
};

/*
 * Enable UART4 Peripheral as defined in: k3-j721e-beagleboneai64-bone-buses.dtsi
 */
&bone_uart_4 {
    status = "okay"; // Enable UART4
};

extlinux.conf bootloader config change:

menu title BeagleBone AI-64 microSD (extlinux.conf) Options

timeout 50

default BeagleBone AI-64 microSD (default)

label BeagleBone AI-64 microSD Recovery
    kernel /Image
    append root=/dev/mmcblk1p2 ro rootfstype=ext4 rootwait net.ifnames=0
    fdtdir /
    initrd /initrd.img

label BeagleBone AI-64 copy microSD to eMMC
    kernel /Image
    append root=/dev/mmcblk1p2 ro rootfstype=ext4 rootwait net.ifnames=0 init=/usr/sbin/init-beagle-flasher
    fdtdir /
    initrd /initrd.img

label BeagleBone AI-64 microSD (default)
    kernel /Image
    append root=/dev/mmcblk1p2 ro rootfstype=ext4 rootwait net.ifnames=0 quiet console=null
    # The "console=null" disables the debug console, which otherwise uses MAIN_UART0
    fdtdir /
    fdtoverlays /overlays/BONE-UART1.dtbo /overlays/BONE-UART2.dtbo /overlays/BONE-UART3.dtbo /overlays/BONE-UART4.dtbo /overlays/BONE-CAN1.dtbo /overlays/BONE-CAN2.dtbo /overlays/BONE-CAN3.dtbo /overlays/BONE-CAN4.dtbo /overlays/BONE-GPIO1.dtbo /overlays/BONE-GPIO2.dtbo
    initrd /initrd.img

Deployment strategy

Transfer all relevant files to the Beaglebone Ai64 target:

#!/bin/bash

#########################################
# Script to Transfer Device Tree Files
# 
# Description:
# - This script transfers the relevant .dts files, extlinux.conf, base .dtsi file,
#   and the GPIO test script to the target device.
# - It also transfers pre and post-reboot automation scripts to the target's home directory.
#
# Usage:
# - Place this script in hw/scripts.
# - Run the script from the hw directory.
# - Provide the target IP address as the first argument when running the script.
#
# Example:
# ./scripts/transfer_dtb_files.sh 172.16.101.21
#
#########################################

# Check if target IP is provided
if [ -z "$1" ]; then
    echo -e "\033[0;31mError: Please provide the target IP as the first argument.\033[0m"
    echo "Usage: $0 <TARGET_IP>"
    exit 1
fi

# Define variables for the target IP and directories
TARGET_IP="$1"
OVERLAYS_DIR="/opt/source/dtb-5.10-ti/src/arm64/overlays"
BASE_DIR="/opt/source/dtb-5.10-ti/src/arm64"
TMP_DIR="/tmp"
HOME_DIR="/home/debian"

# Directories relative to the script's location
SCRIPT_DIR="$(dirname "$0")"
OVERLAYS_PATH="$(realpath "$SCRIPT_DIR/../overlays")"
CONFIGS_PATH="$(realpath "$SCRIPT_DIR/../configs")"
BASE_PATH="$(realpath "$SCRIPT_DIR/../base")"
SCRIPTS_PATH="$(realpath "$SCRIPT_DIR/../scripts")"

# Colored output functions
function print_green() {
    echo -e "\033[0;32m$1\033[0m"
}

function print_red() {
    echo -e "\033[0;31m$1\033[0m"
}

function print_yellow() {
    echo -e "\033[0;33m$1\033[0m"
}

# Files to copy
DTS_FILES=(
    "BONE-CAN1.dts"
    "BONE-CAN2.dts"
    "BONE-CAN3.dts"
    "BONE-CAN4.dts"
    "BONE-UART1.dts"
    "BONE-UART2.dts"
    "BONE-UART3.dts"
    "BONE-UART4.dts"
    "BONE-GPIO1.dts"
    "BONE-GPIO2.dts"
)
AUTOMATION_SCRIPTS=(
    "pre_reboot_setup.sh"
    "post_reboot_verification.sh"
)
EXTLINUX_FILE="extlinux.conf"
DTB_FILE="k3-j721e-beagleboneai64-bone-buses.dtsi"
GPIO_TEST_SCRIPT="setup_and_run_gpio_test.sh"

# Function to copy files
function copy_files() {
    local target_ip="$1"

    # Copy DTS overlay files
    print_yellow "Copying DTS overlay files to target..."
    for dts_file in "${DTS_FILES[@]}"; do
        local source_path="$OVERLAYS_PATH/$dts_file"
        if [ -f "$source_path" ]; then
            scp "$source_path" "debian@${target_ip}:${OVERLAYS_DIR}"
            print_green "Copied $dts_file to ${OVERLAYS_DIR}"
        else
            print_red "$dts_file does not exist in $OVERLAYS_PATH. Skipping."
        fi
    done

    # Copy base DTS file
    local base_dtb_path="$BASE_PATH/$DTB_FILE"
    if [ -f "$base_dtb_path" ]; then
        print_yellow "Copying base DTS file to target..."
        scp "$base_dtb_path" "debian@${target_ip}:${BASE_DIR}"
        print_green "Copied $DTB_FILE to ${BASE_DIR}"
    else
        print_red "$DTB_FILE does not exist in $BASE_PATH. Skipping."
    fi

    # Copy extlinux.conf
    local extlinux_path="$CONFIGS_PATH/$EXTLINUX_FILE"
    if [ -f "$extlinux_path" ]; then
        print_yellow "Copying extlinux.conf to target..."
        scp "$extlinux_path" "debian@${target_ip}:${TMP_DIR}"
        print_green "Copied $EXTLINUX_FILE to ${TMP_DIR}"
    else
        print_red "$EXTLINUX_FILE does not exist in $CONFIGS_PATH. Skipping."
    fi

    # Copy automation scripts to the target's home directory
    print_yellow "Copying automation scripts to target..."
    for script in "${AUTOMATION_SCRIPTS[@]}"; do
        local_script_path="$SCRIPTS_PATH/$script"
        if [ -f "$local_script_path" ]; then
            scp "$local_script_path" "debian@${target_ip}:${HOME_DIR}/"
            print_green "Copied $script to ${HOME_DIR} on the target."
        else
            print_red "$script does not exist in $SCRIPTS_PATH. Skipping."
        fi
    done

    # Copy GPIO test script to the target's home directory
    local gpio_test_script_path="$SCRIPTS_PATH/$GPIO_TEST_SCRIPT"
    if [ -f "$gpio_test_script_path" ]; then
        print_yellow "Copying GPIO test script to target..."
        scp "$gpio_test_script_path" "debian@${target_ip}:${HOME_DIR}/"
        print_green "Copied $GPIO_TEST_SCRIPT to ${HOME_DIR} on the target."
    else
        print_red "$GPIO_TEST_SCRIPT does not exist in $SCRIPTS_PATH. Skipping."
    fi
}

# Run the file copy process
copy_files "$TARGET_IP"

# End script
print_green "File transfer process completed."

Build device tree modifications on the target

#!/bin/bash

#########################################
# Pre-Reboot Setup Script for BeagleBone
#
# Description:
# - Builds and installs device tree files.
# - Updates extlinux.conf with the transferred version.
# - Issues a reboot command.
#########################################

# Password for sudo
PASSWORD="temppwd"

# Directories and files
DTB_DIR="/opt/source/dtb-5.10-ti/"
EXTLINUX_CONF="/boot/firmware/extlinux/extlinux.conf"
TMP_EXTLINUX_CONF="/tmp/extlinux.conf"

# Colored output functions
function print_green() {
    echo -e "\033[0;32m$1\033[0m"
}

function print_red() {
    echo -e "\033[0;31m$1\033[0m"
}

function print_yellow() {
    echo -e "\033[0;33m$1\033[0m"
}

# 1. Build and Install Device Tree Files
print_yellow "Step 1: Building and installing device tree files..."
cd "$DTB_DIR" || { print_red "Failed to change directory to $DTB_DIR"; exit 1; }
echo "$PASSWORD" | sudo -S make clean && make && sudo make install && sync
if [ $? -eq 0 ]; then
    print_green "Device tree build and installation completed successfully."
else
    print_red "Device tree build and installation failed. Exiting."
    exit 1
fi

# 2. Update extlinux.conf
print_yellow "Step 2: Updating extlinux.conf..."
if [ -f "$TMP_EXTLINUX_CONF" ]; then
    echo "$PASSWORD" | sudo -S cp "$TMP_EXTLINUX_CONF" "$EXTLINUX_CONF"
    if [ $? -eq 0 ]; then
        print_green "extlinux.conf updated successfully."
    else
        print_red "Failed to update extlinux.conf. Exiting."
        exit 1
    fi
else
    print_red "Temporary extlinux.conf file not found at $TMP_EXTLINUX_CONF. Exiting."
    exit 1
fi

# 3. Reboot the System
print_yellow "Step 3: Rebooting the system..."
echo "$PASSWORD" | sudo -S reboot
if [ $? -eq 0 ]; then
    print_green "Reboot command issued successfully."
else
    print_red "Failed to issue reboot command. Exiting."
    exit 1
fi

Post reboot, verify the device trees were loaded

#!/bin/bash

#########################################
# Post-Reboot Verification Script
#
# Description:
# - Verifies that the U-Boot and overlays are properly installed.
# - Verifies UART symlinks.
#########################################

# Colored output functions
function print_green() {
    echo -e "\033[0;32m$1\033[0m"
}

function print_red() {
    echo -e "\033[0;31m$1\033[0m"
}

function print_yellow() {
    echo -e "\033[0;33m$1\033[0m"
}

# Expected U-Boot output
EXPECTED_UBOOT_OUTPUT=(
    "UBOOT: Booted Device-Tree:[k3-j721e-beagleboneai64.dts]"
    "UBOOT: Loaded Overlay:[BONE-CAN1.kernel]"
    "UBOOT: Loaded Overlay:[BONE-CAN2.kernel]"
    "UBOOT: Loaded Overlay:[BONE-CAN3.kernel]"
    "UBOOT: Loaded Overlay:[BONE-CAN4.kernel]"
    "UBOOT: Loaded Overlay:[BONE-UART1.kernel]"
    "UBOOT: Loaded Overlay:[BONE-UART2.kernel]"
    "UBOOT: Loaded Overlay:[BONE-UART3.kernel]"
    "UBOOT: Loaded Overlay:[BONE-UART4.kernel]"
    "UBOOT: Loaded Overlay:[BONE-GPIO1.kernel]"
    "UBOOT: Loaded Overlay:[BONE-GPIO2.kernel]"
)

# 1. Verify U-Boot and Overlays
print_yellow "Step 1: Verifying U-Boot and overlays..."
UBOOT_OUTPUT=$(sudo beagle-version | grep UBOOT)
echo "$UBOOT_OUTPUT" | tee /tmp/uboot_verification.log

# Check each expected line in the output
UBOOT_PASS=true
for expected_line in "${EXPECTED_UBOOT_OUTPUT[@]}"; do
    if ! echo "$UBOOT_OUTPUT" | grep -qF "$expected_line"; then
        print_red "Missing expected line: $expected_line"
        UBOOT_PASS=false
    fi
done

if $UBOOT_PASS; then
    print_green "UBOOT verification passed."
else
    print_red "UBOOT verification failed."
    exit 1
fi

# 2. Verify UART Symlinks
print_yellow "Step 2: Verifying UART symlinks..."
UART_OUTPUT=$(for i in /dev/bone/uart/*; do echo "$i is linked to $(readlink -f $i)"; done)
echo "$UART_OUTPUT" | tee /tmp/uart_verification.log

EXPECTED_UART_LINKS=(
    "/dev/bone/uart/1 is linked to /dev/ttyS4"
    "/dev/bone/uart/2 is linked to /dev/ttyS7"
    "/dev/bone/uart/3 is linked to /dev/ttyS0"
    "/dev/bone/uart/4 is linked to /dev/ttyS8"
)

# Check each expected UART symlink
UART_PASS=true
for expected_link in "${EXPECTED_UART_LINKS[@]}"; do
    if ! echo "$UART_OUTPUT" | grep -qF "$expected_link"; then
        print_red "Missing expected UART link: $expected_link"
        UART_PASS=false
    fi
done

if $UART_PASS; then
    print_green "UART symlink verification passed."
else
    print_red "UART symlink verification failed."
    exit 1
fi

print_green "All post-reboot verification steps completed successfully."
exit 0

Relevant resources:

BeagleBone cape interface spec — BeagleBoard Documentation

Additional information:

I’ve created a seperate thread to discuss issues setting up CAN and GPIO peripherals: How can I enable 4xCAN and 2xGPIO on the BeagleBone Ai64

Important information
When testing UART with the minicom utility on the BeagleBone Ai64, make sure to go into the settings everytime you connect to a UART port (ex. sudo minicom -D /dev/bone/uart/4 -b 115200), and set the hardware control off as mentioned by @benedict.hewson above: How can I enable the 5 UARTs of the beaglebone AI-64? - #12 by benedict.hewson